Method for transmitting video data on FPGA and DSP structure on basis of SRIO bus

Abstract

The invention discloses a method for transmitting video data on an FPGA and DSP structure on the basis of an SRIO bus. An FPGA in the method is mainly responsible for video data transmission and video port extension. The video data are transmitted to a DSP chip through the SRIO bus of the FPGA. The design concept of the method mainly includes that only three SRIO services including SWRITE, NREAD and DOORBELL are used during transmission, the video data are reorganized through multiple buffering queues, data units of the video data in the buffering queues, the transmission process and the processing process are stipulated, and the FPGA serves as a control core of SRIO transmission. According to the SRIO transmission method, consumption of FPGA logic resources and storage resources can be reduced, the complexity of SRIO transmission procedures is reduced, parallel control advantages of the FPGA are made full use of, time taken by a DSP in the video transmission process is reduced, and high-speed video transmission is achieved under the condition that few FPGA resources are occupied.

Description

technical field [0001] The invention belongs to the field of embedded video processing, in particular to a low-complexity implementation method for transmitting video data based on an SRIO bus on an FPGA+DSP structure. Background technique [0002] In order to design a video processing system with high processing performance and flexible interface expansion capability, researches on using Field Programmable Gate Array (FPGA) and general-purpose Digital Signal Processor (DSP) as processing cores are gradually increasing. Among them, FPGA can meet the interface requirements in most video processing applications, but when FPGA completes video processing algorithms, program development is difficult and the development cycle is long. In contrast, DSP is a microprocessor dedicated to digital signal processing operations, and its main application is to realize various digital signal processing algorithms in real time and quickly. The FPGA+DSP structure is the core hardware structu...

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Problems solved by technology

The patent application number CN102186076A "a real-time code rate pre-allocated image compression method and image compression device" and the patent application number CN103177455A "method of implementing KLT moving target tracking algorithm based on multi-core DSP" both realize FPGA to DSP SRIO data transmission, the FPGA will package the video data directly to the DSP, and the DSP will do tedious work such as data packet analysis after receiving the data packet, resulting in the DSP not being able to focus on video processing

[0004] The SRIO bus requires the support of the underlying protocol to achieve high-speed and reliable data transmission. DSP manufacturers provide SRIO sample programs with simple interfaces; FPGA manufacturers provide SRIO IP cores, which provide very flexible SRIO control mechanisms and bring benefits to user programming. The user needs to implement the tedious control process of the SRIO IP core

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