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Apparatus and system for interconnecting chips in packages

A chip-in-chip technology, applied in the field of input/output architecture and interface on high-bandwidth packaging

Active Publication Date: 2016-08-24
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Customizing the physical layer design for each different interface requires considerable time and effort

Method used

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  • Apparatus and system for interconnecting chips in packages
  • Apparatus and system for interconnecting chips in packages
  • Apparatus and system for interconnecting chips in packages

Examples

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Embodiment Construction

[0014] Cluster-on-package I / O (OPIO) can be used to provide a customizable interface to couple a chip with one or more other chips without requiring a custom-designed physical layer for interfaces with differently configured features. For example, OPIO can be used to couple a processor and another processor on the same package, or to couple a processor and a memory chip. Other examples include OPIO interfaces using scalable clusters to couple CPUs and caches or different types of other non-memory chips. The coupled chip and OPIO interface can, for example, be in a multi-chip package (MCP) or in a 3D stacked configuration.

[0015] OPIO circuits can be organized into scalable and scalable clusters, and each cluster uses the same physical layer design to meet different interface connection requirements. In one embodiment, a cluster is a group of data transmitters or receivers that share the forwarded clock signal. In one embodiment, the configurable interface features include one...

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Abstract

This document describes devices and systems for controlling traffic on a network-on-a-chip. An embodiment of the device includes a single-ended transmit circuit on a first chip for coupling to a second chip, the transmit circuit having impedance matching and lacking equalization, and a receive circuit lacking equalization, the transmit circuit and the receiving circuit having statically adjustable Features configured and organized in clusters, wherein the clusters have the same physical layer circuit design for different configurations of configurable features, including half-duplex mode and full-duplex mode, wherein the first chip and the second The chips are on the same package, and wherein the plurality of conductive lines for coupling the first chip and the second chip are matched.

Description

Technical field [0001] Embodiments of the present invention relate to input / output architecture and interfaces. More specifically, embodiments of the invention relate to input / output architectures and interfaces on high-bandwidth packages. Background technique [0002] High-bandwidth interconnections between chips using conventional input / output (I / O) interfaces require considerable power and chip area. Therefore, these conventional I / O interfaces are undesirable in applications that require significantly reduced power consumption and / or smaller chip area. [0003] Conventional I / O interfaces limit configurability and scalability due at least in part to their considerable power and chip area requirements. [0004] The conventional I / O interface has a physical layer designed and customized according to the requirements of the interface. Therefore, conventional I / O interfaces with different configurations require different physical layer designs. Customizing the physical layer desi...

Claims

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Application Information

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IPC IPC(8): H04B3/02G06F15/78
CPCH04B14/023G06F15/7825H04B3/02G06F13/4086H03K19/017545G06F13/4068
Inventor T.P.托马斯S.S.库利克R.B.奥斯博恩
Owner INTEL CORP
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