Method for generating SRAM layout

Abstract

The invention provides a method for generating an SRAM layout. The method comprises the steps that firstly, a first unit is formed; secondly, the first unit is copied, so that a second unit is formed; thirdly, the first unit is connected with the second unit, so that an SRAM is formed; finally, identical parameters in the SRAM are grouped, and then the SRAM layout can be automatically generated. In this way, different sizes of SRAM layouts can be effectively generated, design of the SRAM layout is simplified, so that the error rate caused during manual design of the layout is reduced, and the implementation time of the SRAM layout is shortened.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for generating an SRAM layout. Background technique [0002] SRAM (Static Random Access Memory, Static Random Access Memory) is a semiconductor memory that retains data as long as it is powered. SRAM has the advantages of low power consumption, fast data access speed and compatibility with CMOS logic technology, and is widely used in various electronic devices. Therefore, SRAM is an indispensable part of any semiconductor logic process. [0003] A basic SRAM cell consists of two cross-coupled inverters and two access transistors (usually NMOS transistors), which is a typical six-transistor SRAM (6T SRAM). Specifically, the SRAM can be divided into a first inverter (Inverter), a second inverter and two NMOS transistors (abbreviated as NPASS), wherein the first inverter is composed of a first PMOS transistor and a first NMOS transistor, The second inverter is ...

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Problems solved by technology

Although the generation method of the traditional SRAM layout can meet the design requirements of the current SRAM layout, since there are 6 transistors in the SRAM, and each transistor has multiple dimensions that need to be defined, such as gate size, active area size, and injection layer The size of the well layer and the well layer need to be defined. Therefore, the traditional SRAM layout generation method is not efficient, especially when the size of the SRAM needs to be modified, there are many sizes that need to be changed, so human operations often affect the generation of the SRAM layout. Unnecessarily making mistakes and consuming a lot of time and effort

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