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Self-aligned gate structure for field effect transistor

A technology of field effect transistor and gate structure, which is applied in the direction of transistor, semiconductor device, semiconductor/solid-state device manufacturing, etc.

Inactive Publication Date: 2014-09-03
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, even this structure can have two gates on the channel that still overlap the drain causing significant gate-drain capacitance

Method used

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  • Self-aligned gate structure for field effect transistor
  • Self-aligned gate structure for field effect transistor
  • Self-aligned gate structure for field effect transistor

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Experimental program
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Embodiment Construction

[0016] Accordingly, there is a need for field effect transistors with reduced gate-to-drain capacitance to improve device performance. According to various embodiments, gates for power FET products can be produced that will reduce gate-to-drain capacitance by defining self-aligned gates using spacer-style etching. Devices according to various embodiments are functionally similar to STD power FETs, however, the gate only covers the thin oxide region of the channel (p-base), and the polysilicon over the drain region has a thicker oxide , thereby reducing the capacitance.

[0017] A method for forming a spacer gate to reduce the gate-to-drain capacitance of a FET device is discussed below. By reducing the gate length to cover only the channel portion of the device, unnecessary capacitance can be reduced without the need for advanced photolithography. This also eliminates critical alignment requirements in the manufacturing process.

[0018] figure 1 Shown in a conventional t...

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PUM

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Abstract

A field effect transistor has a substrate with an epitaxial layer, base regions extending from a top of the epitaxial layer into the epitaxial layer, an insulation region having side walls and extending between two base regions on top of the substrate; and a polysilicon gate structure covering the insulation region including the side walls, wherein effective gates are formed by a portion of the polysilicon covering side walls above the base region.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of U.S. Provisional Application No. 61 / 570,395, filed December 14, 2011, entitled "SELF-ALIGNED GATE STRUCTURE FOR FIELD EFFECT TRANSISTOR" Interest, said provisional application is hereby incorporated in its entirety. technical field [0003] The present invention relates to field effect transistors, and in particular to gate structures and methods for forming such gates as self-aligned gates. Background technique [0004] Compared to lateral transistors in integrated circuits, power metal oxide semiconductor field effect transistors (MOSFETs) are generally used to handle high power levels. Figure 9 shows a typical MOSFET using a vertically diffused MOSFET structure, also known as a double diffused MOSFET structure (DMOS or VDMOS). [0005] As shown, for example, in FIG. 9, on an N+ substrate 915, an N- epitaxial layer is formed, the thickness and doping of which generally determ...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/66H01L29/423
CPCH01L27/088H01L29/7802H01L29/42376H01L29/66477H01L29/66712H01L21/2815
Inventor 格雷戈里·迪克斯哈罗德·克兰罗德尼·施罗德丹尼尔·J·格里姆
Owner MICROCHIP TECH INC