A Capacitorless Low Dropout Linear Regulator

Abstract

The invention relates to the technical field of electronic circuits, in particular to a non-capacitance low-dropout linear regulator. The present invention includes PMOS tube MP, capacitor C2, resistor R2, buffer, error amplifier and dynamic transconductance enhancement circuit; wherein, the non-inverting input terminal of the buffer is connected to the external reference voltage Vref, and the inverting input terminal and the output terminal of the buffer are interconnected, Its output terminal is connected to the inverting input terminal of the error amplifier; the non-inverting input terminal of the error amplifier is connected to the output terminal of the low-dropout linear voltage regulator, and its output terminal is connected to the output terminal of the dynamic transconductance enhancement circuit; the first dynamic transconductance enhancement circuit The bias terminal VB1 is connected to the first bias terminal of the error amplifier, its second bias terminal VB2 is connected to the second bias terminal of the error amplifier, and its output terminal is connected to the gate of MP. The beneficial effect of the invention is that the transient response in SoC application is improved, and the DTE circuit can provide extra current. The invention is especially suitable for low dropout linear regulators.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a capacitorless low dropout linear regulator (LDO, Low Dropout Regulator). Background technique [0002] Complex SoC (System on Chip) requires multi-voltage and low-noise power supply, and integrating the entire power management system is conducive to simplifying the layout and wiring of the power network and saving system costs. Low-dropout linear regulator is an important research field of power management integrated circuits. The attenuation of high-frequency power supply suppression and load transient response performance is the main problem in the integration process. It is expected to adopt new technologies to make breakthroughs. [0003] In order to obtain an output voltage with fast transient response and low noise, an on-chip capless LDO needs to be integrated into the SoC system. No need for bulky off-chip capacitors saves pin count and board sp...

AI Technical Summary

Problems solved by technology

The traditional slew rate enhancement circuit is non-linear and easy to oscillate

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