Multi-substrate three-dimensional chip packaging method

Abstract

The invention discloses a multi-substrate three-dimensional chip packaging method which is characterized by comprising the steps of integrating and interconnecting a plurality of organic substrates in a chip package, allowing the organic substrates to interconnect bare chips in a plane interconnection manner or a three-dimensional stacking manner, interconnecting the substrates by metal bonding wires, and forming a three-dimensional multi-substrate system chip. The method solves the problem of inadequate wiring resource of a single-substrate system chip, can provides an adequate wiring resource for design of the whole chip, can achieve most functions of a whole system with the single chip, saves a large number of peripheral circuits and components, reduces the design difficulty of the system, and improves the signal integrity of the system.

Description

technical field [0001] The invention belongs to the technical field of system chip design and packaging, in particular to a multi-substrate three-dimensional packaging chip method. According to the function and structure division of the bare chips, the method integrates the bare chips on multiple organic substrates, designs and packages them in a three-dimensional stacking manner, and forms a multi-substrate SiP (system-in-package) chip. Background technique [0002] With the rapid development of the integrated circuit industry, the feature size of chips is getting smaller and smaller, the scale of integration is getting larger and larger, and the functions realized are becoming more and more complex. They are widely used in various industries and become an indispensable part of human life. . However, due to the complex functions of the chip system and the increasingly high requirements for system integration in the industry, the traditional mode of integrating each chip at...

AI Technical Summary

Problems solved by technology

[0004] In the design process of the system chip, designers often encounter the situation that the substrate area cannot meet the design requirements, that is, the total area of ​​the bare chip is larger than the substrate area or the layout cannot meet the wiring requirements

In this case, designers often can only make a compromise by expanding the chip area or cutting system functions. However, such processing methods are contrary to the original intention of the design, and cannot even meet the requirements of users.

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