Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the steps of forming a plurality of fins extending a first direction on a substrate, forming a dummy gate stack structure extending along a second direction on the fins, forming a first part of a gate flank on the two sides of the dummy gate stack structure along the first direction, forming a second part of the gate flank on the two sides of the fins along the second direction, removing the dummy gate stack structure to form a gate trench, and forming a gate stack structure in the gate trench. According to the semiconductor device and the manufacturing method thereof of the invention, residual flanks are formed at the bottoms of the side walls of the fins, so that source and drain contact holes can be effectively filled, filling holes can be reduced or eliminated, and source and drain junctions and run-through leakage of the substrate can be inhibited.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional multi-gate FinFET capable of effectively improving carrier mobility and a manufacturing method thereof. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control ability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness ...

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Problems solved by technology

[0005] However, due to the small size of the FinFET device itself (for example, below 22nm), it is difficult to fill the source-drain contact hole, that is, the metal silicide at the bottom of the Fin sidewall, such as poor shape retention and prone to pores, etc., making it possible to reduce the source-drain contact resistance. hard to accomplish

In addition, due to the close distance to the substrate, for example, there is only a very thin gate insulating layer between the metal silicide and the fin substrate, usually on the order of a few nm, which easily leads to penetration leakage between the source-drain junction and the substrate. , making the device fail

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