nmos transistor and its forming method, cmos transistor and its forming method

Abstract

Provided are an NMOS transistor and a forming method thereof and a CMOS transistor and a forming method thereof. The method for forming the NMOS transistor comprises the steps of providing a substrate which is provided with a pseudo grid structure; forming an interlayer dielectric layer on the substrate, enabling the upper surface of the interlayer dielectric layer to be flush with the upper surface of the pseudo grid structure; removing the pseudo grid structure so as to form a groove in the interlayer dielectric layer; and sequentially forming a high k dielectric layer, a diffusion barrier layer, an N-type work function metal layer and a gate metal layer at the bottom and a side wall of the groove. According to the method for forming the NMOS transistor, the diffusion barrier layer is formed and can prevent aluminum in the N-type work function metal layer from being diffused, the high k dielectric layer can be protected from the damage caused by metal, the time-varying breakdown effect is avoided, and the formed NMOS transistor is more stable and durable.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to an NMOS transistor and a forming method thereof, a CMOS transistor and a forming method thereof. Background technique [0002] In the process node of integrated circuit technology, after the physical gate length reaches below 28 nanometers, high-k materials are usually used as the gate dielectric layer, and the gate last (also known as gate replacement gate) process is used to fabricate the CMOS structure. The gate last process is further divided into high k first (high k first) process and high k last (high k last) process. Since the high k last process can prevent the gate dielectric layer from undergoing high temperature process, the gate last-high k last process becomes Mainstream technology. [0003] The existing CMOS transistor gate-last-last high-k process does not consider NMOS transistors and PMOS transistors separately. NMOS transistors manufactured by existing...

AI Technical Summary

Problems solved by technology

Existing gate-last-last high-k processes for CMOS transistors suffer from high latency between steps and overall process time, and because NMOS transistors have shorter lifetimes, CMOS transistors also have shorter lifetimes

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