Adjustable nonvolatile memory reference unit

Abstract

The invention provides an adjustable nonvolatile memory reference unit, which consists of two lines of serially connected R<X>-NMOS-R<X>-NMOS structures through parallel connection; nonvolatile memory devices M1 and M3 are configured into a low-impedance state, and nonvolatile memory devices M2 and M4 are configured into a high-impedance state, or the nonvolatile memory devices M1 and M2 are configured into the low-impedance state, and the nonvolatile memory devices M3 and M4 are configured into the high-impedance state, and an arithmetic mean value of the electric conductance or the electric resistance of high-low-impedance state memory units is obtained; the top ends of the nonvolatile memory devices M1 and M2 are connected with a bit line BL; source electrodes of NMOS (N-channel Metal Oxide Semiconductor) transistors N3 and N4 are connected with a source electrode line SL; and grid electrodes of NMOS transistors N1 and N2 are connected with a word line WL. In the first scheme, the grid electrodes of the NMOS transistors N3 and N4 are simultaneously connected with an adjustable word line WL, and the design is the rough calibration design. In the second scheme, the grid electrodes of the NMOS transistors N3 and N4 are respectively connected with an adjustable word line WL<A1> and an adjustable word line WL<A2>, and the design is the fine calibration design. The adjustable nonvolatile memory reference unit has the advantages that signals approach to the optimum value; the judgment margin is increased; and the reading reliability is improved.

Description

technical field [0001] The invention relates to an adjustable nonvolatile memory reference unit, which belongs to the technical field of nonvolatile memory. Background technique [0002] In recent years, the rapid development of material physics and electronics has prompted new non-volatile memory technologies, such as Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), Phase Change Random Access Memory (Phase Change Random Access Memory) Memory, PCRAM) and oxide resistive random access memory (Oxide Resistive Random Access Memory, OxRRAM) etc. continue to emerge. A typical nonvolatile memory memory cell consists of a nonvolatile memory device R X , such as Magnetic Tunneling Junction (Magnetic Tunneling Junction, MTJ) or Memristor (Memristor), etc., and an N-type Metal Oxide Semiconductor (N-Metal Oxide Semiconductor, NMOS) transistor in series, as shown in the attached figure 1 shown. where R X There is a low resistance state (the resistance value is recorde...

AI Technical Summary

Problems solved by technology

[0006] Aiming at the problem that the reading circuit of the non-volatile memory mentioned in the above background has low tolerance to process deviation and poor reading reliability, an adjustable non-volatile memory reference unit of the present invention provides a calibrated The reference unit organization method, by adjusting the reference unit, makes the reference signal closer to the theoretical optimal value, thereby increasing the decision margin and improving the reading reliability

Images