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Signal processing circuit, resolver digital converter, and multipath nested mirror amplifier

A technology of signal processing circuit and differential amplifier, applied in amplifiers, differential amplifiers, amplifiers using switched capacitors, etc., can solve problems such as difficulty in ensuring the amplification of input signals and comparison accuracy.

Active Publication Date: 2014-11-26
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] For an amplifier or comparator, it is difficult to ensure the accuracy of amplifying the input signal and comparing it due to the offset voltage generated by the mismatch of its input parts.

Method used

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  • Signal processing circuit, resolver digital converter, and multipath nested mirror amplifier
  • Signal processing circuit, resolver digital converter, and multipath nested mirror amplifier
  • Signal processing circuit, resolver digital converter, and multipath nested mirror amplifier

Examples

Experimental program
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Effect test

no. 1 example

[0038] figure 1 A block diagram of the signal processing circuit 1 according to the first embodiment is shown.

[0039] The signal processing circuit 1 has a chopper amplifier 1A, an adder circuit 1B, and an output stage amplifier 1C. The chopper amplifier 1A has a modulation chopper circuit SA, a first-stage amplifier AMP1 and a demodulation chopper circuit SB. In the modulation chopper circuit SA and the demodulation chopper circuit SB, their chopping operations are controlled by the chopping clock CLK1 output from the control circuit CTL. In the adder circuit 1B, its operation is controlled by the control clock Φ1 and the control clock Φ2 output from the control clock circuit CTL.

[0040] The differential input signal Vsp(t) and the differential input signal Vsm(t) are input into the modulation chopper circuit SA. Upon inverting the logic level of the chopping clock CLK1, the modulating chopper circuit SA is interchanging the differential input signal Vsp(t) applied to...

no. 2 example

[0138] Figure 10 A block diagram of a signal processing circuit 2 according to the second embodiment is shown.

[0139] exist Figure 10 in, is given with figure 1 Parts with the same sign as the sign have the same sign as figure 1 The configuration of the same configuration, and the description of each of these configurations is omitted.

[0140] The signal processing circuit 2 is equivalent to the following configuration so that the adder circuit 2B is replaced by figure 1 The adder circuit in 1B.

[0141] The signal processing circuit 2 has a chopper amplifier 1A, an adder circuit 2B, and an output stage amplifier 1C. The chopper amplifier 1A has a modulation chopper circuit SA, a first-stage amplifier AMP1 and a demodulation chopper circuit SB. In the modulation chopper circuit SA and the demodulation chopper circuit SB, their chopping operations are controlled by the chopping clock CLK1 output from the control circuit CTL. In the adder circuit 2B, its operation...

no. 3 example

[0170] Figure 14 A block diagram of a signal processing circuit 3 according to the third embodiment is shown.

[0171] exist Figure 14 in, is given with figure 1 Parts with the same sign as the sign have the same sign as figure 1 The configuration of the same configuration, and the description of each of these configurations is omitted. That is, the signal processing circuit 3 has a configuration in which in figure 1 In the signal processing circuit 1 shown in , the chopper amplifier 1A is replaced by a chopper amplifier 3A.

[0172] The signal processing circuit 3 has a chopper amplifier 3A, an adder circuit 1B, and an output stage amplifier 1C. The chopper amplifier 3A has a modulation chopper circuit SA and a configuration in which a two-stage single-ended amplifier and a demodulation chopper circuit SB are combined. In the modulation chopper circuit SA and the demodulation chopper circuit SB, their chopping operations are controlled by the chopping clock CLK1 ou...

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PUM

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Abstract

A signal processing circuit includes a chopper amplifier (1) that has a differential amplifier circuit (AMP1) that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit (1B) that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier (1) generates. Differential signals inputted into the differential amplifier circuit (AMP1) are interchanged for every first phase period and second phase period, and the adder circuit (1B) generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2013-103150 filed on May 15, 2013 including the specification, drawings and abstract of the specification is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates to a signal processing circuit and a semiconductor device including the signal processing circuit, such as a semiconductor device including a chopper amplifier. Background technique [0004] For an amplifier or comparator, it is difficult to ensure the accuracy of amplifying the input signal and comparing due to the offset voltage generated from the mismatch of its input parts. [0005] Japanese Unexamined Patent Application Publication No. 2008-219404 discloses an amplifier circuit including a chopper amplifier and an averaging circuit. The averaging circuit samples the output voltage of the chopper amplifier at a plurality of sampling times and generates a...

Claims

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Application Information

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IPC IPC(8): H03F3/45H03F1/26
CPCH03F3/2171H03F2203/45116H03F3/45179H03F3/393H03F2200/271H03F3/005H03F3/45192H03F3/45762H03F2200/264H03F2200/375H03F2200/408H03F2200/411H03F2200/81H03F2203/45012H03F2203/45028H03F2203/45136H03F2203/45138H03F2203/45174H03F2203/45212H03F2203/45512H03F2203/45528H03F2203/45558H03F2203/45594H03F2203/45601H03F2203/45604H03F2203/45631H03F2203/45632H03F2203/45634H03F2203/45641H03F2203/45681H03F2203/45698H03F2203/45726H03F3/45946H03M1/645
Inventor 船户是宏熊本敏夫吉泽知晃黑冈一晃
Owner RENESAS ELECTRONICS CORP
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