A method for implementing gpgpu register cache

An implementation method and register technology, which are applied in the directions of resource allocation, multi-programming device, energy-saving computing, etc., can solve the problems of energy consumption and area waste of GPGPU chips, so as to solve the problem of insufficient number of registers, improve system efficiency, reduce energy consumption and reduce energy consumption. The effect of chip area

Active Publication Date: 2017-10-31
ZHEJIANG UNIV CITY COLLEGE
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  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

The stream processor can only execute some threads in a period of time, and most of the registers saved in the entire register file are idle and will not be used immediately, so the energy consumption and area of ​​the GPGPU chip occupied by these register files are different in time wasted

Method used

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  • A method for implementing gpgpu register cache
  • A method for implementing gpgpu register cache

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Embodiment Construction

[0020] The present invention will be further described below in conjunction with drawings and embodiments.

[0021] The method of the invention includes: adding a register cache in each stream processor to replace a register file, adopting an organization mode based on the register cache, and adopting a scheduling mode based on the register cache for stream processor threads.

[0022] Such as figure 1 As shown, the above-mentioned organization method based on the register cache is as follows:

[0023] A.1) Remove the original register file of the stream processor, save all the register data in the original register file in the memory, add a register cache for storing the registers required by the executing thread in the stream processor, and replace the original There are register files.

[0024] A.2) Load register data from memory to register cache before thread execution.

[0025] When the thread executed by the stream processor needs to access the register file, it acces...

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Abstract

The invention discloses a method for implementing register caches of GPGPU (general purpose graphics processing units). The method includes removing original register files in various stream processors, adding the caches of registers required for storing threads being executed, and loading register data in memories to the register caches before the threads are executed; selecting the thread combinations with the maximum thread quantities from the executable threads on the premise that the registers required by execution of the threads can be stored in the register caches of the stream processors, executing the selected thread combinations, loading register data in the memories to the register caches, selectively executing the threads in the thread combinations in optional modes and reselecting another group of threads when all the threads in the selected thread combinations cannot be executed. The register data are used by each thread in the selected thread combinations. The method has the advantages that storage spaces required by the register files of the stream processors can be reduced, energy consumption and areas can be decreased, the problem of constraints due to insufficient quantities of registers of existing stream processors can be solved, and the system efficiency can be improved.

Description

technical field [0001] The present invention relates to a method for realizing cache, in particular to a method for realizing GPGPU register cache. Background technique [0002] A general-purpose graphics processor GPGPU is a processor that utilizes a graphics processor that traditionally handles graphics tasks to perform general-purpose computing tasks. GPGPU is composed of multiple stream processors. Each stream processor contains multiple computing units. An instruction decoder in the stream processor controls all computing units. The computing units execute instructions in parallel in the manner of single instruction and multiple data, thereby Small management cost to achieve large-scale data parallel computing. The smallest management unit in GPGPU is a thread, and each thread is usually used to process a unit of data in large-scale data. A group of threads in the stream processor are executed in lockstep on the computing unit, called the lockstep execution thread gro...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50
CPCY02D10/00
Inventor 吴明晖俞立呈陈天洲裴玉龙孟静磊
Owner ZHEJIANG UNIV CITY COLLEGE
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