A constant current jfet device and its manufacturing method
A manufacturing method and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of poor constant current accuracy and low cost, and achieve the effect of improved constant current performance and good constant current characteristics
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Embodiment 1
[0055] Both gate regions in this example are formed using three lithography-three different implant energies, specifically:
[0056] Step 1: Select an NTD single wafer with fewer defects. The thickness of the single wafer ranges from 400 to 700 μm, and the resistivity ranges from 0.01 to 0.5 Ω·cm. After marking, cleaning and drying, for example, Figure 5 shown;
[0057] The second step: the first photolithography, first grow a thin oxide layer on the wafer, and then perform the first implantation of the back gate region 2 of the P+ buried layer, specifically implantation with glue, and the ion implantation conditions are: dose 1e15 ~8e18cm -2 , energy 20 ~ 40KeV, such as Figure 6 shown;
[0058] The third step: the second photolithography, the second implantation of the gate region 2 on the back of the P+ buried layer; specifically, implantation with glue is used, and the ion implantation conditions are: dose 1e15-8e18cm -2 , Energy 20~60KeV, such as Figure 7 shown;
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Embodiment 2
[0071] The two gate regions in this example are formed by three times of photolithography - three times of the same implantation energy - different pushing junctions, specifically:
[0072] Step 1: Select an NTD single wafer with fewer defects, with a thickness ranging from 400 to 700 μm and a resistivity ranging from 0.01 to 0.5Ω·cm, marking, cleaning, and drying for later use, such as Figure 5 shown;
[0073] The second step: the first photolithography, first grow a thin oxide layer on the wafer, and then perform the first implantation of the gate region 2 on the back of the P+ buried layer, specifically using glue implantation, the ion implantation conditions are: dose 1e15~ 8e18cm -2 , Energy 20~80KeV, push trap redistribution conditions: anaerobic condition, temperature 950~1000℃, time 25min~30min, such as Figure 6 shown;
[0074] The third step: the second photolithography, the second implantation of the gate region 2 on the back of the P+ buried layer; specifically...
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