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Component embedded package structure and its manufacturing method

A packaging structure, embedded technology, used in semiconductor/solid state device manufacturing, electrical components, semiconductor devices, etc.

Active Publication Date: 2019-06-21
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the semiconductor element is embedded in the substrate, its heat dissipation effect becomes a thorny issue

Method used

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  • Component embedded package structure and its manufacturing method
  • Component embedded package structure and its manufacturing method
  • Component embedded package structure and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0018] Please refer to figure 1 , which shows a cross-sectional view of an embodiment of a device-embedded packaging structure according to the present invention. The component embedded package structure 100 includes a bare chip 102, a substrate 104, a metal layer 106, a first dielectric layer 108, a first patterned conductive layer 110, a second patterned conductive layer 112, a third patterned conductive layer 114 and solder mask 116.

[0019] The die 102 has an active face 102a, a back face 102b opposite to the active face 102a, and a side face 102c. The backside 102 b of the die 102 is in direct contact with the metal layer 106 .

[0020] The substrate 104 has a first surface 104a and a second surface 104b opposite to the first surface 104a. In an embodiment, the substrate 104 has at least one first via 104c extending from the first surface 104a to the second surface 104b for receiving at least one die. The width and shape of the first through holes 104c are designed a...

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PUM

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Abstract

The invention relates to a component embedded packaging structure and a manufacturing method thereof. The component embedded package structure includes: a substrate having a first surface and a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; A permanent interconnect extending from the first surface to the second surface; a first patterned conductive layer is disposed on the first surface; a second patterned conductive layer is disposed on the second surface, transparent Electrically connected to the first patterned conductive layer through the first electrical interconnection; at least one die is disposed in the through hole, the die has an active surface and an active surface relative to the active surface a backside, the backside of the die is exposed on the second surface of the substrate; a first dielectric layer, filling the gap between the die and the sidewalls of the vias and covering the die The active surface of the substrate and the first surface of the substrate; the third patterned conductive layer is disposed on the surface of the first dielectric layer, electrically connected to the die through the second electrical interconnection connections; and a metal layer disposed directly on the backside of the die.

Description

technical field [0001] The present invention relates to a semiconductor package and its manufacturing method. Background technique [0002] In response to the demand for small size and performance of electronic products, the design of the key components of electronic products, that is, semiconductor elements, is becoming more and more complex and required to be more miniaturized. Generally speaking, semiconductor components are mounted on a substrate containing circuits and then packaged. However, in this way, the space on the substrate is partially occupied by the semiconductor package, reducing the possibility of further stacking chips. Therefore, the current technology research and development direction is towards embedding components in the substrate to reduce the space occupied by semiconductor components on the substrate and simplify the assembly process. However, since the semiconductor element is embedded in the substrate, its heat dissipation effect becomes a diff...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/367H01L21/50H01L21/56H01L21/60
CPCH01L23/3128H01L23/49816H01L23/49827H01L23/49838H01L21/561H01L24/19H01L24/20H01L21/568H01L2224/04105H01L2224/12105H01L2224/73267H01L2924/18162H01L2924/19105H01L23/36H01L2224/131H01L2224/16227H01L2224/32245H01L2924/15153H01L2924/15313H01L2924/3025H01L2924/3511H01L2224/9222H01L2224/16235H01L23/5389H01L23/552H01L23/5383H01L25/16H01L21/4857H01L2924/014H01L2924/00014H01L2224/18H01L2224/16225H01L21/486H01L21/6835H01L23/13H01L23/5384H01L23/5386H01L24/13H01L24/16H01L25/0657H01L25/50H01L2221/68318H01L2221/68345H01L2221/68359H01L2224/13022H01L2224/13024H01L2224/16147H01L2224/215H01L2224/24145H01L2225/06517H01L2225/06589H01L2924/01013H01L2924/01022H01L2924/01028H01L2924/01029H01L2924/0105H01L2924/01079
Inventor 李志成
Owner ADVANCED SEMICON ENG INC
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