Segmented digital-to-analog converter having weighted current sources
A technology of analog converters and currents, applied in the field of methods and corresponding control logic, capable of solving problems such as nonlinearity
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[0063] For purposes of illustration, a specific embodiment of the DAC100 is shown in the Image 6 , where the number of segmentation levels is n=3, and the total resolution is N bits. The decoding logic (see Tables 1-3) and design conditions to adjust the weighting coefficients in the transfer function (see Equations 13 to 15) are discussed below and can be extended to any n>1.
[0064] When n=3, the digital input is divided into three sub-codewords dM, dP and dL with respective lengths M, P and L, where N=M+P+L. Sub-DACs are provided for each sub-word: most significant bit (MSB) sub-DAC, partly significant bit (PSB) sub-DAC and least significant bit (LSB) sub-DAC.
[0065] VLSB = VREFH - VREFL 2 N - - - ( 8 )
[0066] Applying Equation 3, the transfer function ...
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