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TEST SYSTEM AND semiconductor DEVICE

A testing system and testing machine technology, applied in semiconductor/solid-state device testing/measurement, electrical measurement, measurement device, etc., can solve problems such as inability to transfer wafers with bias voltage, misjudgment of wafers, failure to confirm burn-in steps, etc.

Active Publication Date: 2015-01-14
ELITE SEMICON MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the controller cannot confirm whether the burn-in step is actually performed
For example, there may be a short circuit or an open circuit between the controller and the die, so that the bias voltage cannot be transmitted to the die
Therefore, the burn-in step is not actually completed, and the controller may misidentify defective wafers in the subsequent CP test step

Method used

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  • TEST SYSTEM AND semiconductor DEVICE
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  • TEST SYSTEM AND semiconductor DEVICE

Examples

Experimental program
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Embodiment Construction

[0020] The present invention discloses a test system for performing a wafer level burn-in test. The "wafer-level burn-in test" here means that the chip will undergo a continuity test at the wafer level, followed by a burn-in step, and finally a CP test step to screen out defects before packaging of wafers.

[0021] figure 1 A block diagram of a test system 100 for performing a wafer-level burn-in test incorporating an embodiment of the present invention is shown. Such as figure 1 As shown, the test system 100 includes a test system controller 10, which can be an automatic test equipment (Automatic Test Equipment, ATE) or a general-purpose computer. The test system controller 10 is connected to a test head 14 via a communication cable 12 .

[0022] The test head 14 may include a base 16 to which a probe card 18 is connected. The probe card 18 serves as an interface between the test head 14 and a wafer 22 to be tested. The probe card 18 can contact the wafer 22 to be teste...

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PUM

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Abstract

An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on a wafer during a wafer level burn-in testing. According to one embodiment of the present invention, the test system comprises a probe card and n chips. The probe card comprises m first signal contacts for receiving m test signals from the tester, n second signal contacts for providing n test results to the tester, and a contact array. The probe card is in contact with the chips on the wafer through a plurality of needles. In this manner, the test system can detect whether the continuity fault condition exists in the path between the tester and the chips on the wafer during the wafer level burn-in testing.

Description

technical field [0001] The present invention relates to a test system and a semiconductor device implemented in the test system. Background technique [0002] In a conventional integrated circuit (Integrated Circuit, IC) manufacturing process, a plurality of dispersed ICs are formed on a semiconductor wafer in the form of chips or dice. When the manufacturing process is complete, the wafer is diced to separate it into individual chips. Each die is then packaged into modules or incorporated into larger systems. [0003] Due to inherent defects in the wafer, or defects in one or more steps in the manufacturing process, some packaged chips may not perform as intended. These defects may show up early or may not show up until the wafer has been in operation for a while. In order to identify these defective wafers, a burn-in step is performed on the wafer. During the burn-in step, the wafer is heated to a high temperature, and a test controller statically or dynamically applie...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/02H01L21/66
Inventor 许人寿吴柏勋
Owner ELITE SEMICON MEMORY TECH INC