[0064] Example one
[0065] An embodiment of the present invention provides an array substrate, including a base substrate, a gate metal layer, a gate insulating layer, an active layer, a source and drain metal layer, a passivation layer, and a common electrode layer sequentially formed on the base substrate , And a pixel electrode layer located between the active layer and the source and drain metal layer or between the source and drain metal layer and the passivation layer; the gate metal layer includes a gate electrode and a common electrode line;
[0066] The pixel electrode layer or the source and drain metal layer includes a connecting electrode, the connecting electrode is electrically connected to the common electrode line through the first via hole on the gate insulating layer, and the connecting electrode is connected to the common electrode layer through the second via hole on the passivation layer. The common electrode is electrically connected.
[0067] In the embodiment of the present invention, by providing a connecting electrode on the pixel electrode layer or the source and drain metal layer, the connecting electrode is electrically connected to the common electrode line through the first via hole, and the common electrode of the common electrode layer is electrically connected to the connecting electrode through the second via hole. Connect to realize the electrical connection between the common electrode and the common electrode line. Since the first via and the second via are electrically connected through the connecting electrode, the depth and size of the first via and the second via are compared to the direct The hole depth and size of the continuous via holes penetrating the gate insulating layer and the passivation layer are reduced, which reduces the impact on the coating film layer in the subsequent preparation process and avoids the coating film layer ripples.
[0068] In this embodiment, the connecting electrode is in direct contact with the gate metal layer and the passivation layer, and passes through the first via hole on the gate metal layer and the second via hole on the passivation layer, respectively, with the common electrode line and the common electrode line. The electrodes are electrically connected. Preferably, the vertical projections of the first via and the second via on the base substrate are staggered, the first via corresponds to the position of the common electrode line, the second via corresponds to the position of the common electrode, and the first via corresponds to the position of the common electrode. The vertical projection of the second via hole on the base substrate falls within the range of the vertical projection of the connection electrode on the base substrate. Since the vertical projections of the first via and the second via are not at the same position, they do not affect each other.
[0069] Preferably, the connection electrode is located on the pixel electrode layer, and the connection electrode and the pixel electrode of the pixel electrode layer are insulated from each other. Alternatively, the connection electrode is located in the source and drain metal layer, and the connection electrode is insulated from the source electrode, the drain electrode and the data line of the source and drain metal layer.
[0070] In order to understand the present invention more clearly, in this embodiment, the hierarchical arrangement of the pixel electrode layer and the source and drain metal layers, and the specific structure including the connection electrodes on the pixel electrode layer and the source and drain metal layers are described as follows:
[0071] See figure 2 , An embodiment of the present invention provides an array substrate, including a base substrate 1, a gate metal layer, a gate insulating layer 4, an active layer 5, a pixel electrode layer, a source and drain metal layer formed on the base substrate 1 in sequence Layer, passivation layer 10 and common electrode layer; the gate metal layer includes the gate electrode 2 and the common electrode line 3, the pixel electrode layer includes the pixel electrode 6, the source and drain metal layer includes the source electrode 7, the drain electrode 8 and the data line 9. The common electrode layer includes a common electrode 11, and the source electrode 7, the drain electrode 8, the gate electrode 2, and the active layer 5 constitute a thin film transistor (TFT).
[0072] The pixel electrode layer further includes a connection electrode 12, which is electrically connected to the common electrode line 3 through a first via 13 on the gate insulating layer, and the connection electrode 12 is electrically connected to the common electrode layer through a second via 14 on the passivation layer. The common electrode 11 is electrically connected. In this embodiment, the connecting electrode 12 and the pixel electrode 6 are arranged in the same layer.
[0073] according to figure 2 , The connecting electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10, and is arranged outside the active layer 5 and the pixel electrode 6 area.
[0074] The vertical projections (not shown) of the first via 13 and the second via 14 on the base substrate 1 are staggered. The first via 13 corresponds to the position of the common electrode line 3, and the second via 14 corresponds to the common electrode. The position of 11 corresponds to the vertical projection (not shown) of the first via 13 and the second via 14 on the base substrate 1 falling on the vertical projection (not shown) of the connecting electrode 12 on the base substrate 1. Within the scope, although the above projections are not shown in this embodiment, figure 2 The positional relationship of the first via hole 13, the second via hole 14 and the connection electrode 12 is visually shown. Since the vertical projections of the first via 13 and the second via 14 are not at the same position, they do not affect each other.
[0075] Preferably, the connection electrode 12 and the pixel electrode 6 are insulated from each other.
[0076] In this embodiment, by providing a connection electrode 12 on the pixel electrode layer, the connection electrode 12 is electrically connected to the common electrode line 3 through the first via hole 13, and the common electrode 11 of the common electrode layer passes through the The second via hole 14 is electrically connected to the connection electrode 12 to realize the electrical connection between the common electrode 11 and the common electrode line 3. Because the first via hole 13 and the second via hole 14 pass through The connection electrode 12 realizes electrical connection, so the hole depth and size of the first via 13 and the second via 14 are compared with directly penetrating the gate insulating layer 4 and the passivation layer 10 Continuous vias (such as figure 1 The shown via hole 20) has a reduced hole depth and size, which reduces the impact on the coating film layer in the subsequent preparation process, avoids the generation of coating film layer ripples, and improves the yield of the array substrate.
[0077] See image 3 , An embodiment of the present invention provides an array substrate, including a base substrate 1, a gate metal layer, a gate insulating layer 4, an active layer 5, a pixel electrode layer, a source and drain metal layer formed on the base substrate 1 in sequence Layer, passivation layer 10 and common electrode layer; the gate metal layer includes the gate electrode 2 and the common electrode line 3, the pixel electrode layer includes the pixel electrode 6, the source and drain metal layer includes the source electrode 7, the drain electrode 8 and the data line 9. The common electrode layer includes the common electrode 11, and the source electrode 7, the drain electrode 8, the gate electrode 2, and the active layer 5 constitute a TFT.
[0078] The source and drain metal layer also includes a connection electrode 12, which is electrically connected to the common electrode line 3 through a first via 13 on the gate insulating layer, and the connection electrode 12 is electrically connected to the common electrode line 3 through a second via 14 on the passivation layer. The common electrode 11 of the electrode layer is electrically connected. In this embodiment, the connection electrode 12 is arranged in the same layer as the source electrode 7, the drain electrode 8 and the data line 9.
[0079] according to image 3 , The connecting electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10, and is arranged outside the active layer 5 and the pixel electrode 6 area.
[0080] The vertical projections (not shown) of the first via 13 and the second via 14 on the base substrate 1 are staggered. The first via 13 corresponds to the position of the common electrode line 3, and the second via 14 corresponds to the common electrode. The position of 11 corresponds to the vertical projection (not shown) of the first via 13 and the second via 14 on the base substrate 1 falling on the vertical projection (not shown) of the connecting electrode 12 on the base substrate 1. Within the scope, although the above projections are not shown in this embodiment, image 3 The positional relationship of the first via hole 13, the second via hole 14 and the connection electrode 12 is visually shown. Since the vertical projections of the first via 13 and the second via 14 are not at the same position, they do not affect each other.
[0081] Preferably, the connection electrode 12 is insulated from the source electrode 7, the drain electrode 8 and the data line 9 from each other.
[0082] In this embodiment, by providing connection electrodes 12 on the source and drain metal layers, the connection electrodes 12 are electrically connected to the common electrode lines 3 through the first via holes 13, and the common electrode 11 of the common electrode layer The electrical connection between the common electrode 11 and the common electrode line 3 is achieved through the second via 14 and the connection electrode 12, because the first via 13 and the second via 14 The electrical connection is achieved through the connection electrode 12. Therefore, the hole depth and size of the first via 13 and the second via 14 are compared to those directly penetrating the gate insulating layer 4 and the passivation layer 10. Two layers of continuous vias (such as figure 1 The shown via hole 20) has a reduced hole depth and size, which reduces the impact on the coating film layer in the subsequent preparation process, avoids the generation of coating film layer ripples, and improves the yield of the array substrate.
[0083] See Figure 4 , An embodiment of the present invention provides an array substrate, including a base substrate 1, a gate metal layer, a gate insulating layer 4, an active layer 5, a source and drain metal layer, and a pixel electrode that are sequentially formed on the base substrate 1. Layer, passivation layer 10 and common electrode layer; the gate metal layer includes the gate electrode 2 and the common electrode line 3, the pixel electrode layer includes the pixel electrode 6, the source and drain metal layer includes the source electrode 7, the drain electrode 8 and the data line 9. The common electrode layer includes the common electrode 11, and the source electrode 7, the drain electrode 8, the gate electrode 2, and the active layer 5 constitute a TFT.
[0084] The source and drain metal layer also includes a connection electrode 12, which is electrically connected to the common electrode line 3 through a first via 13 on the gate insulating layer, and the connection electrode 12 is electrically connected to the common electrode line 3 through a second via 14 on the passivation layer. The common electrode 11 of the electrode layer is electrically connected. In this embodiment, the connection electrode 12 is arranged in the same layer as the source electrode 7, the drain electrode 8 and the data line 9.
[0085] according to Figure 4 , The connecting electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10, and is arranged outside the active layer 5 and the pixel electrode 6 area.
[0086] The vertical projections (not shown) of the first via 13 and the second via 14 on the base substrate 1 are staggered. The first via 13 corresponds to the position of the common electrode line 3, and the second via 14 corresponds to the common electrode. The position of 11 corresponds to the vertical projection (not shown) of the first via 13 and the second via 14 on the base substrate 1 falling on the vertical projection (not shown) of the connecting electrode 12 on the base substrate 1. Within the scope, although the above projections are not shown in this embodiment, image 3 The positional relationship of the first via hole 13, the second via hole 14 and the connection electrode 12 is visually shown. Since the vertical projections of the first via 13 and the second via 14 are not at the same position, they do not affect each other.
[0087] Preferably, the connection electrode 12 is insulated from the source electrode 7, the drain electrode 8 and the data line 9 from each other.
[0088] In this embodiment, by providing connection electrodes 12 on the source and drain metal layers, the connection electrodes 12 are electrically connected to the common electrode lines 3 through the first via holes 13, and the common electrode 11 of the common electrode layer The electrical connection between the common electrode 11 and the common electrode line 3 is achieved through the second via 14 and the connection electrode 12, because the first via 13 and the second via 14 The electrical connection is achieved through the connection electrode 12. Therefore, the hole depth and size of the first via 13 and the second via 14 are compared to those directly penetrating the gate insulating layer 4 and the passivation layer 10. Two layers of continuous vias (such as figure 1 The shown via hole 20) has a reduced hole depth and size, which reduces the impact on the coating film layer in the subsequent preparation process, avoids the generation of coating film layer ripples, and improves the yield of the array substrate.
[0089] See Figure 5 , An embodiment of the present invention provides an array substrate, including a base substrate 1, a gate metal layer, a gate insulating layer 4, an active layer 5, a source and drain metal layer, and a pixel electrode that are sequentially formed on the base substrate 1. Layer, passivation layer 10 and common electrode layer; the gate metal layer includes the gate electrode 2 and the common electrode line 3, the pixel electrode layer includes the pixel electrode 6, the source and drain metal layer includes the source electrode 7, the drain electrode 8 and the data line 9. The common electrode layer includes a common electrode 11, and the source electrode 7, the drain electrode 8, the gate electrode 2, and the active layer 5 constitute a thin film transistor (TFT).
[0090] The pixel electrode layer further includes a connection electrode 12, which is electrically connected to the common electrode line 3 through a first via 13 on the gate insulating layer, and the connection electrode 12 is electrically connected to the common electrode layer through a second via 14 on the passivation layer. The common electrode 11 is electrically connected. In this embodiment, the connecting electrode 12 and the pixel electrode 6 are arranged in the same layer.
[0091] according to Figure 5 , The connecting electrode 12 is in direct contact with the gate insulating layer 4 and the passivation layer 10, and is arranged outside the active layer 5 and the pixel electrode 6 area.
[0092] The vertical projections (not shown) of the first via 13 and the second via 14 on the base substrate 1 are staggered. The first via 13 corresponds to the position of the common electrode line 3, and the second via 14 corresponds to the common electrode. The position of 11 corresponds to the vertical projection (not shown) of the first via 13 and the second via 14 on the base substrate 1 falling on the vertical projection (not shown) of the connecting electrode 12 on the base substrate 1. Within the scope, although the above projections are not shown in this embodiment, figure 2 The positional relationship of the first via hole 13, the second via hole 14 and the connection electrode 12 is visually shown. Since the vertical projections of the first via 13 and the second via 14 are not at the same position, they do not affect each other.
[0093] Preferably, the connection electrode 12 and the pixel electrode 6 are insulated from each other.
[0094] In this embodiment, by providing a connection electrode 12 on the pixel electrode layer, the connection electrode 12 is electrically connected to the common electrode line 3 through the first via hole 13, and the common electrode 11 of the common electrode layer passes through the The second via hole 14 is electrically connected to the connection electrode 12 to realize the electrical connection between the common electrode 11 and the common electrode line 3. Because the first via hole 13 and the second via hole 14 pass through The connection electrode 12 realizes electrical connection, so the hole depth and size of the first via 13 and the second via 14 are compared with directly penetrating the gate insulating layer 4 and the passivation layer 10 Continuous vias (such as figure 1 The shown via hole 20) has a reduced hole depth and size, which reduces the impact on the coating film layer in the subsequent preparation process, avoids the generation of coating film layer ripples, and improves the yield of the array substrate.
