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A Layout Pattern Decomposition Method for Triple Exposure Photolithography Process

A technology of triple exposure and photolithography technology, which is applied in special data processing applications, instruments, electrical digital data processing, etc., and can solve problems such as the decline in chip yield

Active Publication Date: 2017-10-10
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

How to assign the GDSII design layout patterns to multiple different masks, so that the pattern conflicts on the same mask are the least, is the key to the multi-exposure layout allocation method; at the same time, in order to reduce the number of conflicts, the same layout pattern may It will be divided and assigned to different masks, and the division points on the same pattern are called stitches; practice shows that too many stitches will lead to a decrease in chip yield

Method used

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  • A Layout Pattern Decomposition Method for Triple Exposure Photolithography Process
  • A Layout Pattern Decomposition Method for Triple Exposure Photolithography Process
  • A Layout Pattern Decomposition Method for Triple Exposure Photolithography Process

Examples

Experimental program
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Effect test

Embodiment 1

[0073] The pattern in the input layout file is as Figure 7 As shown, it needs to be assigned with a triple exposure layout pattern. Among them 1, 2, 3, 4 are polygon layout patterns. Set the number of iterations n s =30, the number of consecutive no updates t=3, the weight coefficient of the conflict side w c =10, weight coefficient w of stitched edges s = 1.

[0074] Follow the described step 1.1 to Figure 7 The polygon in is cut into several rectangles, such as Figure 8 Shown. Among them, polygon 2 is cut into rectangles 21 and 22, and polygon 4 is cut into rectangles 41 and 42. Follow step 1.2 to extend the side of each rectangle by b / 2, and then construct a conflict graph according to the method described in step 1.3 to step 1.4. The result is as follows Figure 8 As shown, the rectangles are expressed as vertices in the conflict graph, the solid lines indicate that there are conflicting edges between the rectangles, and the edge weights are positive, and the dashed lines...

Embodiment 2

[0086] The method of the present invention is implemented by C++ programming language, and runs on a 64-bit 2.66GHz central processing unit and a Linux machine with 4GB of memory. The test layout comes from the first metal layer layout in the ISCAS-85&89 test case. Set the collision distance b=160nm, and the collision edge weight coefficient W c =10, weight coefficient of stitching edge W s =1, the number of iterations n s = 30, the number of consecutive no updates t = 3; the experimental results are shown in Table 1, where #C, #S, COST, and imp respectively represent the number of conflicts after the layout is decomposed by the method of the present invention, the number of stitching points, the objective function and the present invention The COST improvement ratio of the corresponding method. Compared with the two methods in the prior art document [8] and document [9], the improvement effect of the method of the present invention can reach up to 29% and 42.2% respectively (t...

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Abstract

The invention belongs to the field of manufacturability design of semiconductor photolithography process, and particularly relates to a layout pattern decomposition method of triple exposure photolithography process. Firstly, the method of rectangular expansion is used to construct the conflict graph; then the initial solution of three coloring is randomly generated, one color is fixed in turn in each round of optimization, and the conflicting subgraph of the remaining two colors is optimized by double exposure pattern allocation method, and the iteration is repeated. The optimization process is performed until the current optimal solution is not updated for several times; finally, the above steps are called repeatedly and the optimal three-colored result is selected as the output. The present invention adopts the existing double exposure pattern distribution method, adopts multiple calculations to select the optimal strategy, finds the global optimal solution, and achieves the purpose of allocating layout patterns for the triple exposure lithography process.

Description

Technical field [0001] The invention belongs to the field of semiconductor photolithography process manufacturability design, and specifically relates to a layout pattern decomposition method of a triple exposure photolithography process. In this method, dense layout patterns are distributed to three different mask plates, which can meet the requirements of semiconductor Lithography process requirements. Background technique [0002] The prior art discloses that the photolithography process is one of the key processes in the integrated circuit manufacturing process. As the feature size of integrated circuits continues to shrink, the density of layout patterns continues to increase, but the wavelength of the light source used in lithography has not been significantly reduced, and the exposure resolution has not been significantly improved. This leads to pattern conflicts on the same mask. ) The number continues to increase. The pattern conflict is defined as the distance between...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50G06F9/44
Inventor 曾璇陆伟成周海严昌浩张业
Owner FUDAN UNIV