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Edge Termination Structures with Trench Isolation Regions

An edge termination and trench technology, applied in the direction of semiconductor devices, electrical components, circuits, etc.

Active Publication Date: 2017-05-17
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The phenomenon of avalanche breakdown limits the ability of pn junctions to support high voltages

Method used

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  • Edge Termination Structures with Trench Isolation Regions
  • Edge Termination Structures with Trench Isolation Regions
  • Edge Termination Structures with Trench Isolation Regions

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Embodiment Construction

[0017] In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and show, by way of illustration, specific embodiments in which the invention may be practiced. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0018] refer to Figures 1A to 1D An embodiment of a method for producing an edge termination structure in a semiconductor body is explained in the following. Figures 1A to 1D Each illustrates a vertical cross-sectional view of a segment of the semiconductor body 100 . refer to Figures 1A to 1D , the semiconductor substrate 100 includes a first surface 101 . exist Figures 1A to 1D The vertical cross-sectional view shown in FIG. 2 shows the semiconductor substrate 100 in a cross-sectional plane that is substantially normal to the first surface 101 .

[0019] The semiconductor body 100 (wh...

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PUM

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Abstract

The present invention relates to edge termination structures having trench isolation regions. A semiconductor device includes a semiconductor body and an edge termination structure. The edge termination structure includes a first oxide layer, a second oxide layer, a semiconductor mesa region between the first oxide layer and the second oxide layer, and a first segment included in the semiconductor mesa region and in the semiconductor mesa region The doped field region of the second segment in the region below the region. The second segment overlaps the first and second oxide layers in a region below the semiconductor mesa region.

Description

technical field [0001] Embodiments of the invention relate to methods for producing edge termination structures in semiconductor devices, and to semiconductor devices having edge termination structures. Background technique [0002] Power semiconductor devices such as power diodes, power MOSFETs or power IGBTs are designed to withstand high blocking voltages. These power devices contain a pn junction formed between a p-doped semiconductor region and an n-doped semiconductor region. The device blocks (is off) when the pn junction is reverse biased. In this case, the depletion region (space charge region) propagates in the p-doped and n-doped regions. Usually one of the n-doped and p-doped semiconductor regions is more lightly doped than the other of the semiconductor regions, so that the depletion region extends mainly in the more lightly doped region, which is more lightly doped The region primarily supports the voltage applied across the pn junction. [0003] The phenom...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
CPCH01L29/0619H01L29/063H01L29/66348H01L29/66712H01L29/66734H01L29/7397H01L29/7811H01L29/7813H01L29/0615H01L29/1095H01L29/7395H01L21/761
Inventor A.布赖梅泽尔E.格里布尔O.赫伯伦A.莫泽尔H-J.舒尔策S.福斯
Owner INFINEON TECH AG