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Design method of cache coherence protocol for multi-core and multi-processor platform

A multi-processor and design method technology, applied in the fields of electrical digital data processing, instruments, calculations, etc., can solve the problems of reducing protocol performance and increasing system communication burden, so as to improve synchronization efficiency, reduce message synchronization delay, and simplify processing Effect

Active Publication Date: 2017-09-29
INSPUR BEIJING ELECTRONICS INFORMATION IND
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  • Claims
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Problems solved by technology

It can be seen that the traditional Cache consistency protocol (such as the MESI protocol) uses a single shared state (ie: S state), because it is impossible to distinguish whether the data is shared within one synchronization domain or shared by multiple synchronization domains at the same time, therefore, in order to ensure Cache consistency When performing data synchronization, some non-essential synchronization messages need to be sent, which increases the communication burden of the system and reduces the performance of the protocol

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  • Design method of cache coherence protocol for multi-core and multi-processor platform
  • Design method of cache coherence protocol for multi-core and multi-processor platform
  • Design method of cache coherence protocol for multi-core and multi-processor platform

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Embodiment Construction

[0018] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0019] Depending on the implementation, the processor can be implemented using a bus-snooping-based or directory-based Cache coherence protocol. The description of the embodiments of the present invention takes bus monitoring as an example to describe, and the directory is used to record shared information between processors.

[0020] In this embodiment, with figure 1 The shown multi-core multi-processor structure is used as an example to illustrate the synchronization process of Cache lines in the S and SS states and the mutual conversion between the SS and S shared states. For concise and accurate description, use (processor number, processing core number) to represent a processor core. For example, (0,1) indicates the processor core numbered 1 of processor 0, (1,0) indicates the processor core numbered 0 of processor 1, and so on. dL1 represents the pri...

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Abstract

The invention discloses a design method of a high-speed cache (Cache) coherence protocol oriented to a multi-core multiprocessor platform, wherein the Cache lines located in two Cache coherence synchronization domains have two shared states, and the two shared states They are respectively used to indicate the sharing status of the Cache line in the two Cache consistency synchronization domains. The design method of the multi-core multi-processor platform-oriented Cache consistency protocol disclosed by the present invention can reduce the number of data synchronization messages caused by partial write operations and invalid operations, reduce the delay of data synchronization messages, and thereby improve the data synchronization efficiency of the protocol.

Description

technical field [0001] The invention relates to the field of computer system structure, in particular to a design method of a high-speed cache (Cache) coherence protocol oriented to a multi-core multi-processor platform. Background technique [0002] Multi-core multi-processor platforms have become a common computer architecture. In this structure, the multi-core multi-processor system is composed of a plurality of processors, and each processor has at least two processor cores. Inside the processor, each processor core usually has a private data / instruction cache, and may share the last level cache. For example, if figure 1 As shown, the multi-core multi-processor system includes two processors (processor 0 and processor 1), and each processor has two processor cores, and each processor core has a private separate data / instruction L1 Cache, At the same time, the two processor cores inside the processor share a unified L2 Cache. [0003] In the above system, inside the p...

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Application Information

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IPC IPC(8): G06F15/163G06F13/42
Inventor 王恩东倪璠陈继承
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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