Non-volatile semiconductor storage device

Abstract

Proposed is a non-volatile semiconductor storage device with which, while effecting miniaturization, it is possible to suppress a disturb occurrence better than before. In a non-volatile semiconductor storage device, forming a plurality of words in a matrix, disposing a power source unit for each word line column (memory well), imparting a different unit voltage to each power source unit corresponding to whether a selected memory well is present in a given word line column, switching on a word line unit basis a switch mechanism of each power source unit according to a control line voltage value, and individually imparting to each word line either a charge storage gate voltage or a charge storage interdiction gate voltage, it is possible to freely set for each word line column a charge storage interdiction gate voltage value or a bit line voltage value which is capable of suppressing a disturb occurrence. A plurality of power source units are connected to a common control line in the row direction, obviating the need for a separate address decoder for each word column line, and allowing effecting miniaturization.

Description

technical field [0001] The present application relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of writing data to predetermined memory cells among a plurality of memory cell transistors arranged in a matrix (hereinafter simply referred to as memory cells). device. Background technique [0002] In the prior art, as a nonvolatile semiconductor memory device, for example, a nonvolatile semiconductor memory device in which data is written by storing charges in a charge storage layer of a memory cell according to quantum tunneling is disclosed (for example, refer to Patent Document 1 and non-patent literature 1). it's here, Figure 13 Shown is a conventional nonvolatile semiconductor storage device 501, which has the following structure: including, for example, a plurality of P-type storage grooves W503a, W503b, W503c, and W503d arranged in the row direction (left-right direction), and each P-type s...

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Problems solved by technology

Thus, in each unselected memory cell C2 in the third region AR503 where the unselected byte and the selected row intersect, although the write gate voltage of 12V is applied to the control gate from the selected common word line 515, since the The non-selected first bit line L1c and the non-selected second bit line L2c apply a write inhibit voltage of 12V to one end and the other end, therefore, the voltage becomes the same between the control gate and the channel region, and as a result, quantum tunneling does not occur effect, so charge will not be injected into the charge storage layer, which may become a state where data cannot be written

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