FPGA (field programmable gate array) based high-speed eMMC (embedded multimedia card) array controller

Abstract

The invention discloses an FPGA (field programmable gate array) based high-speed eMMC (embedded multimedia card) array controller, comprising a high-speed eMMC array controller IP (internet protocol) core, wherein the high-speed eMMC array controller IP core is realized on an FPGA, is provided with a user management interface and a user data interface and is respectively connected with a data cache RAM (random access memory) and a plurality of eMMC chipsets; each eMMC chipset consists of a plurality of eMMC chips which are mounted on a same eMMC bus. The FPGA based high-speed eMMC array controller has the beneficial effects that the potential performances of each eMMC chip can be effectively released; the data throughout is balanced by built-in / externally-extended caching, and the eMMC chips are subjected to packet pipeline operation, so that the maximum consecutive storage bandwidth is realized, and simple and easy-to-use front end data input / output interfaces are provided. The FPGA based high-speed eMMC array controller is applied to application locations, such as high frequency collecting record, communication data record and bus data record, with high requirements on the memory capacity, the bandwidth and the reliability.

Description

technical field [0001] The present invention relates to the technical field of array controllers, in particular to an FPGA-based high-speed eMMC array controller Background technique [0002] FPGA (Field-Programmable Gate Array), that is, Field Programmable Gate Array. Its characteristics are as follows: 1) ASIC circuits (application-specific integrated circuits) are designed using FPGA, and users can obtain suitable chips without putting them into production. 2) FPGA can be used as a sample piece of other full-custom or semi-custom ASIC circuits. 3) There are abundant flip-flops and I / O pins inside the FPGA. 4) FPGA is one of the devices with the shortest design cycle, the lowest development cost and the lowest risk in ASIC circuits. 5) FPGA adopts high-speed CMOS technology, low power consumption, and can be compatible with CMOS and TTL levels. It can be seen that the FPGA chip is one of the best choices for small batch systems to improve system integration and reliabi...

AI Technical Summary

Problems solved by technology

Disadvantages: low bandwidth (the internal bus bandwidth of the processor is limited and shared with the CPU core), the data interface cannot be customized (usually data / address bus, etc.), and the capacity is low (usually only 1 to 2 eMMC memory chips can be mounted);

Disadvantages: single data interface (usually SATA, USB, etc., not easy to integrate in the device), poor scalability (the number of eMMC memory chips mounted is limited, usually less than 16 pieces), continuous bandwidth is not guaranteed (designed for general occasions, not for Sequential read / write is specially optimized), its price is still far from the price of traditional flash memory cards or flash memory chips

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