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Over-etching rate test structure, forming method thereof and over-etching rate measurement method

A technology of testing structure and over-etching, which is applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve problems such as cumbersome process, and achieve the effect of simplifying complexity

Active Publication Date: 2015-03-18
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0018] The problem solved by the present invention is that in the prior art, the process of measuring the overetching rate δ is cumbersome

Method used

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  • Over-etching rate test structure, forming method thereof and over-etching rate measurement method
  • Over-etching rate test structure, forming method thereof and over-etching rate measurement method
  • Over-etching rate test structure, forming method thereof and over-etching rate measurement method

Examples

Experimental program
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Effect test

no. 1 example

[0071] This embodiment provides a method for forming a test structure for overetching rate, including:

[0072] refer to Figure 7 , a substrate 110 is provided, and the substrate 110 includes a first region 111 and a second region 112 located at different positions.

[0073] The substrate 110 may be a semiconductor substrate known in the art such as a silicon substrate, a silicon germanium substrate, or the like. Semiconductor devices such as transistors, interconnection lines, and plugs may also be formed in the substrate 110 .

[0074] The substrate 110 also includes a chip area (not shown), and the first area 111 and the second area 112 are located outside the chip area.

[0075] In order to save the occupied area of ​​the first area 111 and the second area 112 , the first area 111 and the second area 112 are in contact. Figure 7 In order to distinguish, the first area 111 and the second area 112 are separated by a straight line.

[0076] In other embodiments, the fir...

no. 2 example

[0123] This embodiment provides a test structure, refer to Figure 15 ,include:

[0124] a substrate 110, the substrate 110 comprising a first region 111 and a second region 112 at different positions;

[0125] a first interlayer dielectric layer 121 located on the first region 111;

[0126] A second interlayer dielectric layer 122 located on the second region 112, the thickness of the second interlayer dielectric layer 122 is smaller than the thickness of the first interlayer dielectric layer 121;

[0127] A first etch stop layer 131 located on the second interlayer dielectric layer 122, the upper surface of the first etch stop layer 131 is flush with the upper surface of the first interlayer dielectric layer 121;

[0128] The third interlayer dielectric layer 123 located on the first etching stop layer 131 and the first interlayer dielectric layer 121, the first interlayer dielectric layer 121, the second interlayer dielectric layer 122 and the third interlayer dielectric ...

no. 3 example

[0138] This embodiment provides a method for measuring the overetching rate.

[0139] refer to Figure 15 , providing the test structure of the overetch rate formed by the first embodiment.

[0140] The first through hole 161 and the second through hole 162 are in the shape of a truncated cone with a larger top and a smaller bottom.

[0141] Since the first through hole 161 is not blocked by the first etch stop layer 131 , it is etched into the first interlayer dielectric layer 121 , and the depth of the bottom of the first through hole 161 entering the first interlayer dielectric layer 121 is S3 .

[0142] Since the bottom of the first through hole 161 will be etched into the first interlayer dielectric layer 121, the bottom of the first through hole 161 will not increase due to lateral etching, and the diameter of the bottom of the first through hole 161 remains b1 . Since the top opening of the first through hole 161 does not have a mask layer of a corresponding size, th...

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Abstract

The invention relates to an over-etching rate test structure, a forming method thereof and an over-etching rate measurement method, wherein the over-etching rate test structure comprises a substrate, a first interlayer dielectric layer, a second interlayer dielectric layer, a first etching stop layer, a third interlayer dielectric layer, a first trench, a second trench, a first through hole and a second through hole; the substrate comprises a first area and a second area; the first interlayer dielectric layer is located on the first area; the second interlayer dielectric layer is located on the second area; the first etching stop layer is located on the second interlayer dielectric layer, and the upper surface of the first etching stop layer is flushed with the upper surface of the first interlayer dielectric layer; the third interlayer dielectric layer is located on the first etching stop layer and the first interlayer dielectric layer; the first trench is located in the third interlayer dielectric layer on the first area; the second trench is located in the third interlayer dielectric layer on the second area; the first through hole is shaped like a big-end-up truncated cone; the second through hole is shaped like a big-end-up truncated cone. The test structure provided by the invention can decrease the complexity of over-etching rate measurement.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a test structure for an over-etch rate, a forming method thereof, and a method for measuring the over-etch rate. Background technique [0002] In the field of semiconductor manufacturing, with the development of technology, the size of semiconductor devices is getting smaller and the complexity is getting higher and higher. In order to ensure the reliability of semiconductor devices, it is necessary to strictly control the manufacturing process of semiconductor devices. [0003] Taking the etching method of the dielectric layer in the process of forming the copper damascene structure as an example, it mainly includes the following steps: [0004] refer to figure 1 , providing a substrate 1, forming a first interlayer dielectric layer 21 on the substrate 1, forming an interconnection line 3 on the first interlayer dielectric layer 21, and forming a second interlayer dielectric layer...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/528H01L21/768H01L23/544
Inventor 周俊卿孟晓莹张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP
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