Shift register as well as driving method thereof, gate driving circuit and display device

Abstract

The embodiment of the invention discloses a shift register as well as a driving method of the shift register, a gate driving circuit and a display device, and relates to the technical field of display. The influence on an output signal by the change of a clock signal associated with an output module can be reduced, and an output effect of the shift register is improved. The shift register comprises an input module, an output module and an output control module, wherein the output module comprises a first output unit and a second output unit; a first node is used for controlling the first output unit; the first output unit is used for controlling signal transmission between a signal input end and a signal output end of a second clock signal; a second node is used for controlling the second output unit, and the second output unit is used for controlling signal transmission between a signal input end and a signal output end of a high level; the output control module comprises a first control unit and a second control unit, wherein the first control unit is used for controlling the level of the first node, and the second control unit is used for controlling the level of the second node.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a shift register, a driving method thereof, a gate driving circuit, and a display device. Background technique [0002] In order to realize normal display of the display device, the display device needs to include a gate driving circuit. Specifically, the gate driving circuit includes a plurality of shift registers cascaded with each other. [0003] Specifically, the structure of the shift register is as figure 1 As shown, the shift register includes an input module, an output module and an output control module, wherein the input module includes M1, the output module includes M2 and M3, and the output control module includes M4, M5, C1 and C2, wherein M1-M5 are all PMOSFET turned on for low level. The timing diagram of its working process is as follows: figure 2 As shown, in the t1 stage, the start signal input by the start signal input terminal STV and the first c...

AI Technical Summary

Problems solved by technology

[0004] The inventors found that when the second clock signal input by the second clock signal input terminal CK2 changes, the signal on the gate of M2 will be affected by the coupling capacitance formed...

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