Gate drive circuit, drive method of gate drive circuit, array substrate and display device

Abstract

The invention provides a gate drive circuit. The gate drive circuit comprises at least one set of clock signal lines and multiple stages of cascaded shifting deposit units. Each set of clock signal lines include two clock signal lines. The shifting deposit units are divided into at least one set. Each set of clock signal lines correspond to one set of shifting deposit units. One clock signal line in each set of clock signal lines is connected with the reset signal input end of the last stage of shifting deposit unit in the set of shifting deposit units corresponding to the set of clock signal lines. The invention further provides an array substrate, a display device and a drive method of the gate drive circuit. Clock signals input through the clock signal lines are reset signals provided by the shifting deposit units serving as reset units. Thus, no additional reset units or additional thin film transistors need to be added to the gate drive circuit, the overall structure of the gate drive circuit is simplified, and the narrow frame design of the display device can be easily achieved.

Description

technical field [0001] The present invention relates to the field of display devices, in particular, to a gate driving circuit, a driving method for the gate driving circuit, an array substrate including the gate driving circuit, and a display device. Background technique [0002] The gate drive circuit realizes the shift register function. The gate drive circuit includes multiple groups of shift register units. For each group of three consecutive shift register units, the second shift register unit uses It is used to input the third shift register unit and reset the first shift register unit to realize the function of sequential output. Therefore, the first shift register unit needs to add an additional start signal STV for initial input of each frame, and the last shift register unit also needs to perform additional reset control to realize normal shutdown. [0003] figure 1 and figure 2 It is a schematic diagram of cascaded gate drive circuits commonly used at present...

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This will also increase the bezel width and IC cost

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