Method and circuit for improving setup time and hold time margin of sequential device input signal

Abstract

The invention relates to a circuit for improving the setup time and holding time margin of an input signal of a sequential device, which has a first input terminal, a second input terminal and an output terminal, the first input terminal inputs the input signal, and the second input terminal Input a first clock signal, the output terminal is connected to the sequential device, the first clock signal is also the clock signal of the sequential device, the circuit includes: a first delay unit, the first delay unit inputs the first clock signal and After a delay of a first predetermined time, a second clock signal is output; a first latch, the data end of the first latch is connected to the input signal, and the clock end of the first latch is connected to the second clock signal , the output terminal of the first latch outputs a first stretching signal, and the first stretching signal is to stretch the width of the active level in the input signal backward.

Description

technical field [0001] The invention relates to a digital circuit, in particular to a method and a circuit for improving the setup time and the hold time margin of an input signal of a sequential device. Background technique [0002] With the development of electronic technology, the operating frequency of digital electronic systems is getting higher and higher, and the requirements for the timing relationship of signals are becoming more and more stringent. In order to ensure that the digital electronic system can work stably, it is necessary to test the timing parameters of the sequential devices in the system. These timing parameters include signal setup time (setup time) and hold time (hold time). [0003] The setup time and hold time are the time requirements for testing sequential devices between input signals (such as digital signals, address signals, chip select signals, etc.) and clock signals, which characterize the input duration of data before and after clock ed...

AI Technical Summary

Problems solved by technology

[0006] However, in actual digital electronic systems, there may still be individual sequential devices or circuits that require a long setup time and / or hold time. As a result, the sum of setup time and hold time is very close to one clock cycle

In this case, through the aforementioned relative relationship adjustment between the input signal and the clock signal, although it is possible to meet the requirements of the setup time and the hold time at the same time, such a tight timing design means that there is no margin to deal with the deviation of the actual chip ( On ChipVariation, OCV), such as clock signal jitter (jitter) and skew (skew), which may lead to poor system stability

[0007] Faced with the aforementioned problems, some digital electronic systems have to reduce the clock frequency and increase the clock period to meet the requirements of setup time and hold time, at the cost of sacrificing the performance of the system

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