Receiver, differential receiver, and analog front-end circuits for high-speed serial interfaces

Abstract

The invention discloses an analog front end circuit of a differential receiver for a high-speed serial interface. The analog front end circuit comprises an impedance matching unit, a differential amplifier and an amplitude detection judging unit, wherein the impedance matching unit is used for adapting to input signals of different amplitudes and realizing multiplexed output of the input signals; the differential amplifier is used for amplifying the output signals of the impedance matching unit and providing the amplified signals to the amplitude detection judging unit; the amplitude detection judging unit is used for detecting the amplitude of the output signals of the differential amplifier, judging whether the amplitude of the output signals of the differential amplifier is greater than the preset amplitude threshold value, and selecting one of the multiplexed output of the impedance matching unit to be connected with the differential amplifier according to the judgment result. The invention further discloses the differential receiver and a receiver for the high-speed serial interface, which can be suitable for input signals within a wider band range, and are simple in structure and prone to realize.

Description

technical field [0001] The invention relates to the technical field of integrated circuit high-speed serial communication interfaces, in particular to a receiver for high-speed serial interfaces, a differential receiver and an analog front-end circuit thereof. Background technique [0002] When the frequency of the parallel signal line increases, the skew between the signal and the clock edge is more and more stringent. At the same time, the number of parallel bus pins increases, which increases the cost of chip packaging and testing and the complexity of PCB routing. The clock in the serial bus is encoded in the serial data stream, which not only saves the transmission of CLOCK for synchronization, but also does not have the signal skew problem of the parallel bus. The reduction in the number of pins and wires also reduces the cost of the chip and the layout of the PCB. The complexity avoids the interference of the clock on the transmitted data signal, and at the same time ...

AI Technical Summary

Problems solved by technology

Depending on the speed of the high-speed serial interface, the input signal amplitude range is very large, and the large input signal makes it difficult for the analog front-end circuit of the differential receiver in the prior art to work normally, and causes serious distortion of the output signal

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