A High Speed ​​Current Sensitive Amplifier Applied in SRAM Circuit

Abstract

The present invention provides a sensitive amplifier, which at least includes: a current isolation circuit for isolating input signals and output signals; a current amplification circuit connected to the current isolation circuit for amplifying the input current and outputting a corresponding voltage signal; The step-down circuit in the current amplifying circuit is used to step down the signal output by the current amplifying circuit; the latch circuit connected to the step-down circuit is used to latch the signal output by the step-down circuit ; A bias circuit connected to the latch circuit for providing bias to the latch circuit. The high-speed current sensitive amplifier of the invention not only has simple sequence control, but also effectively shortens the reading time of the sensitive amplifier, is suitable for static random access memory circuit design, and is especially suitable for high-speed design. In addition, based on the 0.13 micron SOI CMOS process, the simulation results show that when the high level of the output voltage of the sense amplifier is 70% of VDD, the required time is 51pS.

Description

technical field [0001] The invention belongs to the technical field of memory design and relates to the design of a static random access memory reading circuit, in particular to a high-speed current sensitive amplifier applied to a static random access memory circuit. Background technique [0002] Static random access memory is a volatile memory, because its peripheral control circuit is relatively simple, and its reading and writing speed is fast, so it is widely used in the cache part of the processor; it is common in car equipment, smart equipment, network equipment, etc. The peripheral circuit of SRAM is mainly composed of address decoding circuit, write drive circuit, sense amplifier, read output and data selection circuit; among them, the sense amplifier is the most critical peripheral circuit. [0003] In the SRAM circuit, each pair of bit lines may have dozens or even hundreds of memory cells, so the load capacitance of the bit lines is relatively large, especially i...

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Problems solved by technology

[0008] It can be seen from the above that when the sensing current is small, the reading speed of the sense amplifier is slow; that is, the high level of the output terminal SO and SOB voltage transitions to the high level of the output terminal SO and the low level of the output terminal SOB (or vice versa). After a period of time, it is difficult to apply in high-speed SRAM circuit design

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