High-speed current sensitive amplifier applied to static random access memory circuit

Abstract

The invention provides a sensitive amplifier, and discloses a high-speed current sensitivity amplifier applied to a static random access memory circuit. The high-speed current sensitivity amplifier at least comprises a current isolation circuit, a current amplification circuit, a voltage reduction circuit, a latch circuit and an offset circuit, wherein the current isolation circuit is used for isolating input signals from output signals; the current amplification circuit is connected with the current isolation circuit and is used for amplifying input current and used for outputting corresponding voltage signals; the voltage reduction circuit is connected with the current amplification circuit and is used for reducing voltage of signals output from the current amplification circuit; the latch circuit is connected with the voltage reduction circuit and is used for latching signals outputted from the voltage reduction circuit; the offset circuit is connected with the latch circuit and is used for providing offset for the latch circuit. The high-speed current sensitivity amplifier is not only simple in time-sequence control, but also applicable to design of a static random access memory circuit, and particularly applicable to high-speed design, and the reading time of the sensitive amplifier can be effectively shortened; in addition, based on an SOI CMOS process of 0.13 micrometer, the simulation result shows that it takes 51pS to output voltage high-level of 70%VDD by the sensitive amplifier.

Description

technical field [0001] The invention belongs to the technical field of memory design and relates to the design of a static random access memory reading circuit, in particular to a high-speed current sensitive amplifier applied to a static random access memory circuit. Background technique [0002] Static random access memory is a volatile memory, because its peripheral control circuit is relatively simple, and its reading and writing speed is fast, so it is widely used in the cache part of the processor; it is common in car equipment, smart equipment, network equipment, etc. The peripheral circuit of SRAM is mainly composed of address decoding circuit, write drive circuit, sense amplifier, read output and data selection circuit; among them, the sense amplifier is the most critical peripheral circuit. [0003] In the SRAM circuit, each pair of bit lines may have dozens or even hundreds of memory cells, so the load capacitance of the bit lines is relatively large, especially i...

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Problems solved by technology

[0008] It can be seen from the above that when the sensing current is small, the reading speed of the sense amplifier is slow; that is, the high level of the output terminal SO and SOB voltage transitions to the high level of the output terminal SO and the low level of the output terminal SOB (or vice versa). After a period of time, it is difficult to apply in high-speed SRAM circuit design

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