32results about How to "Simple timing control" patented technology

An image reading apparatus for reading indicia on the front and back surfaces of a document using two image sensors includes a document detection sensor to detect the document, a first image sensor for reading an image on one surface of the document, a second image sensor for reading an image on the other surface of the document, and a controller. The controller starts to read the image data from the first and second image sensors when prescribed amounts of time have passed after the document detection sensor detects the leading edge of the document, and stops the reading of the image data from the image sensors. The structure provides a lightweight and compact apparatus while reducing image noise caused by the mutual interferences of the light sources in reading the image data.

An apparatus for generating digital data. A signal regenerated by a playback head is sequentially processed by an analog filter, A / D, and an interpolator, and is provided to a digital equalizer. The digital equalizer has a plurality of variable filters connected in parallel. While the characteristic of the first variable filter is adjusted, the interpolator performs timing control using the output of the second variable filter. After the adjustment is completed, the switch SW is switched to perform timing control of the interpolator using the output of the first variable filter. Thus, capable of varying the equalization processing characteristics of a digital signal and facilitating the timing adjustment of an interpolator at the same time.

An image capturing apparatus is provided. A synchronizing signal generation unit generates a short-term vertical synchronizing signal VDS and a long-term vertical synchronizing signal VDL, one cycle of which is equal to N cycles of VDS. An exposure control unit performs short-term exposure and long-term exposure for the predetermined number of lines of an image sensor according to VDS and VDL. The exposure control unit starts a read operation of pixel signals for a long-term exposure line in synchronism with VDL, and starts a read operation of pixel signals for a short-term exposure line in synchronism with VDS, which does not overlap a read period Fr_L Readout of pixel signals of a long-term exposure line.

The embodiment of the present invention discloses a simple calibration scheme for the capacitance mismatch error of the pipeline analog-to-digital converter. On the basis of the traditional non-calibration pipeline analog-to-digital converter structure, it consists of a stage MDAC structure and a stage calibration switch structure that needs to be calibrated The calibration stage of the capacitance mismatch error, meanwhile, increases the digital calibration circuit of the capacitance mismatch error. During the calibration stage capacitance error extraction work, two specific inputs are given to the calibration stage sampling capacitor through the stage calibration switch structure, and two digital codes containing capacitance mismatch errors are obtained, and then the calibration stage capacitance mismatch error is extracted based on them And perform digital calibration. The capacitance mismatch error calibration solution has an extremely simple structure, extremely few additional components, and extremely simple timing control, and can effectively calibrate the problem of static characteristic degradation caused by capacitance mismatch.

The invention discloses a CT image reconstruction back-projection acceleration method based on a genetic algorithm, which overcomes the problems of limited memory access bandwidth and low self-adaptive degree in the implementation mode of accelerating CT reconstruction back-projection by using CUDA in the prior art. Under the CUDA programming framework of this invention, the CUDA-based back-projection parallel computing strategy is as follows: (1) One back-projection kernel function operation processes multiple projections; (2) Reasonably design the thread grid (grid) and thread block (block) The dimensions and order of the global memory are guaranteed to be merged and accessed; (3) Use the constant memory to save the constant in the back projection; (4) Use the texture memory to realize bilinear interpolation and reduce the operation time of arithmetic instructions; (5) Reduce the back projection The same factor in the projection operation. The invention does not need to be identified manually, and the acceleration strategy has a high degree of self-adaptation.

The invention relates to an improved scan chain unit and a non-concurrent testing method based on the same, which belongs to the filed of on-chip system testing and aims at solving the problems that the existing scan chain-based non-concurrent on-line testing method has strict requirements for time sequences, is difficult to control and can not realize the one-step import of multiple groups of test vectors. The improved scan chain unit is used for replacing a D trigger in an on-chip system, and the unit contains two triggers and two selectors, wherein a first trigger is a basic unit which composes the original circuit scan chain and is used for realizing the function same with that of the original D trigger, and a second trigger is introduced for saving data in the testing process; and the two data selectors control the flow direction of data by means of enable ends, a first selector is used for controlling whether data in the second trigger can be transmitted to the first trigger, and a second selector is used for controlling the working state or the scanning state of the first trigger. Thus, multiple groups of test vectors can be input to the unit for continuous testing, and therunning state of the circuit is not changed before and after the test.

The invention discloses a test circuit and a method for testing the on-off characteristics of a converter valve. In the test circuit, the positive pole of the DC power supply in the energy supplement circuit is connected to the anode of the first thyristor; one end of the recovery valve in the recovery circuit is respectively connected to the One end of the inductor is connected to the cathode of the first thyristor, and the other end of the recovery valve is connected to the negative pole of the DC power supply; one end of the H bridge circuit in the output circuit is connected to the other end of the inductor, and the other end of the H bridge circuit is connected to the negative pole of the DC power supply. The circuit includes: a first sub-module including a first capacitor and a first switch component and a second sub-module including a second capacitor and a second switch component, the capacitance of the first capacitor and the second capacitor are different; the load circuit includes a The valve test object, the valve test object to be tested is connected to the two ends of the H-bridge circuit. Through the implementation of the invention, a test platform capable of periodic operation and whose turn-on voltage is different from the turn-off voltage can be built, so that the turn-on and turn-off characteristics of valves and the electrical performance of internal components can be tested in a targeted manner.

The invention discloses a SPAD array-level readout circuit adopting quadratic correlation double-sampling technology, which includes a CDS readout circuit and a sample-and-hold circuit. The first-stage CDS readout circuit consists of a voltage follower, two switch circuits and a sampling capacitor, which are connected to each column bus to ensure fast readout of the information of the pixel unit, and the information in the pixel unit Fixed pattern noise cancellation. The second-stage CDS readout circuit consists of 2 voltage followers, 2 switch circuits and 2 sampling capacitors, which are used to eliminate fixed pattern noise in the readout circuit. The quadratic correlation double-sampling array-level readout circuit only needs two control signals, and the timing signal is simple. The invention has the advantages of simple timing control and fast readout speed. The two-stage CDS only needs two control signals, and the readout speed is fast, which improves the working efficiency of the readout circuit. Therefore, it has obvious advantages in large-scale pixel array circuits.

The invention discloses a geometric size measuring method and a device for a slit inside free-form surface. The geometric size measuring method for the slit inside free-form surface comprises the steps of acquiring a slit image: conducting the segmented acquisition of the slit image of a to-be-measured free-form surface product; processing the slit image: processing each segment of the acquired slit image so as to obtain a slit cross-sectional profile, and positioning the edge feature points of each segment of the slit profile, the inflection point of the slit profile, the highest point of the slit profile and the lowest point of the slit profile; conducting the registering and splicing operation: registering and splicing all segments of the processed slit profile; conducting the segmented fitting operation: conducting the segmented fitting for the feature points of the slit profile after the registering and splicing operation so as to obtain an overall slit profile containing the lowest-point curve, the edge curve and the highest-point curve of a slit; and acquiring the geometric size of the slit: according to the fitted curve, acquiring the depth, the length and the width of the slit.

The invention discloses an AMBE2000 control system, comprising an analog / digital converter, an AMBE2000 encoder, an FPGA, an AMBE2000 decoder, and a digital / analog converter; Multiplexing, receiving configuration signals during configuration, and receiving normal decoded data (channel code stream) after configuration, thus greatly simplifying the timing control of AMBE2000; at the same time, the invention also discloses a control method of AMBE2000, which controls the configuration clock and The data is processed to determine whether the configuration is completed, so as to switch the chip pins. This method is simple and convenient.

Provided are an array substrate gate driving circuit, a driving method thereof, and a display device. The array substrate gate drive circuit includes at least one shift register group, each shift register group includes a plurality of shift registers cascaded together, the plurality of shift registers include a first shift register, and the connection position is at a second shift register after the first shift register and a third shift register connected after the second shift register, wherein the third shift register is provided with an initialization terminal, and the The initialization terminal is connected to the output terminal of the first shift register.

The invention discloses a parallel interface sequential control device which is positioned at an analog baseband or digital baseband. The device comprises the following modules: a control module used for receiving control information from a system and status indication information from an opposite-end baseband and generating a control sequence and a status indication signal according to the control information and the status indication information, wherein the control sequence can control a channel multiplexing module to send data and control a channel demultiplexing module to receive data and the status indication signal indicates the data sending / receiving status; the channel multiplexing module used for sending first data through a two-channel to the opposite-end baseband according to the control sequence when the status indication signal indicates the sending status; and the channel demultiplexing module used for receiving second data from the opposite-end baseband through the two-channel according to the control sequence when the status indication signal indicates the receiving status. According to the invention, interface sequential control complexity is simplified, and power consumption is minimized.

The present invention provides a sensitive amplifier, which at least includes: a current isolation circuit for isolating input signals and output signals; a current amplification circuit connected to the current isolation circuit for amplifying the input current and outputting a corresponding voltage signal; The step-down circuit in the current amplifying circuit is used to step down the signal output by the current amplifying circuit; the latch circuit connected to the step-down circuit is used to latch the signal output by the step-down circuit ; A bias circuit connected to the latch circuit for providing bias to the latch circuit. The high-speed current sensitive amplifier of the invention not only has simple sequence control, but also effectively shortens the reading time of the sensitive amplifier, is suitable for static random access memory circuit design, and is especially suitable for high-speed design. In addition, based on the 0.13 micron SOI CMOS process, the simulation results show that when the high level of the output voltage of the sense amplifier is 70% of VDD, the required time is 51pS.