Embedded dynamic random access memory unit and its forming method
A memory unit, dynamic random technology, applied in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., to achieve the effect of small chip area and improved integration
Active Publication Date: 2017-11-03
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0005] In summary, the integration level of the embedded DRAM in the prior art still needs to be further improved
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[0032] As mentioned in the background art, the integration degree of the embedded DRAM formed in the prior art is not high, and the occupied chip area is relatively large.
[0033] In the existing embedded DRAM, the logic area and the storage area are formed on the semiconductor substrate at the same time, which needs to occupy a large chip area, resulting in a low integration level of the embedded DRAM.
[0034] In the embodiment of the present invention, the transistors in the storage area are formed on the top of the logic area, so that the chip area occupied by the embedded DRAM can be reduced.
[0035] In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0036] Please refer to figure 1 , providing a semiconductor substrate 100 .
[0037] The material of the semiconductor substrate 100 can b...
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Abstract
An embedded dynamic random access memory and a forming method thereof, the forming method of the embedded dynamic random access memory comprising: providing a semiconductor substrate, forming a logic transistor on the semiconductor substrate, and covering a first dielectric layer of the logic transistor; A first metal plug is formed in the first dielectric layer; a second dielectric layer is formed on the surface of the first dielectric layer, and a first metal interconnection structure in the second dielectric layer is formed, and the first metal interconnection structure is connected to the second dielectric layer. A metal plug; a storage transistor is formed on the surface of the second dielectric layer, and a third dielectric layer, and the second source or second drain on one side of the storage transistor is located on the surface of the first metal interconnection structure; on the third dielectric layer A second metal interconnection structure is formed in the layer, and the second metal interconnection structure is connected to the second drain or the second source on the other side of the storage transistor; a capacitor is formed on the surface of the second metal interconnection structure. The forming method can improve the integration degree of the embedded dynamic random access memory.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to an embedded dynamic random access memory unit and a forming method thereof. Background technique [0002] Embedded memory is a system-on-a-chip device, and memory and logic devices are formed on the same chip to reduce manufacturing costs. The embedded memory device includes a storage area and a logic area, and the data stored in the storage area is operated by the logic circuit in the logic area. At present, more extensive memory devices include: DRAM units, SRAM units and flash memory units. [0003] The DRAM unit mainly includes: a storage transistor and a capacitor. In the prior art, the storage transistors and capacitors of the DRAM unit are formed in a stacked structure, so as to improve the integration degree of the DRAM unit. [0004] Since the storage transistors of the DRAM unit and the transistors in the logic circuit all need to be formed in the semiconducto...
Claims
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IPC IPC(8): H01L27/108H01L21/8242
Inventor 三重野文健
Owner SEMICON MFG INT (SHANGHAI) CORP