A Design Method of Digital Marker in Test Layout

Abstract

The present invention relates to a design method of a digital mark in a test layout, comprising: step (a) first directly defining a non-key layer digital mark, wherein the non-key layer digital mark has a relatively large length and width; step (b) Multiple virtual patterns of key layers are inserted into the non-key layer digital mark area to form recognizable key layer digital marks. In order to solve the problem in the prior art that the special pattern of the digital mark causes process defects, the invention provides a brand-new layout digital mark design method. The digital mark design method defines a digital mark through non-critical layers, and then fills the digital mark area with a universally existing dummy pattern to form a recognizable uniform digital mark including all physical layers. A more uniform pattern can be obtained throughout the layout by the described setting.

Description

technical field [0001] The invention relates to the field of semiconductors, and in particular, the invention relates to a design method for digital marks in a test layout. Background technique [0002] Integrated circuit manufacturing technology is a complicated process, and the technology is updated very quickly. A key parameter characterizing integrated circuit manufacturing technology is the minimum feature size, namely critical dimension (CD). With the continuous development of semiconductor technology, the critical dimensions of devices are getting smaller and smaller. It is precisely because of the reduction of critical dimensions that it is possible to set millions of devices on each chip. [0003] Design for Manufacturability (DFM) has become increasingly important in the semiconductor industry nano-design process methodology. The DFM refers to a unified description of the rules, tools and methods in chip design for the purpose of rapidly improving the production ...

AI Technical Summary

Problems solved by technology

like figure 1 As shown in the figure, the design of the digital marks described in the prior art is not distinguished from design critical layers (active area / gate / metal layer M1-M8, AA / GT / M1-M8) and non-critical layers (No. A top metal layer and / or a second top metal layer, TM1 / TM2) patterns, key layers and non-key layer digital marks are designed to directly define numbers with larger widths and lengths as digital marks, since the digital marks (numerical marker) has a large width and length and includes a lot of small convex corners (jog), so it will cause: key layer chemical mechanical polishing (CMP) process to form dishing, increase the key layer optical proximity effect Difficulty of correcting processing, weakening process windows of photolithography and etching; in addition, it will also reduce the overall uniformity of the layer pattern

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