FPGA (field programmable gate array) based method and FPGA based device for adjusting MIPI (mobile industry processor interface) signal transmission

Abstract

The invention discloses an FPGA (field programmable gate array) based method and an FPGA based device for adjusting MIPI (mobile industry processor interface) signal transmission. According to the method, time sequences needed by MIPI clock and data transmission are configured and controlled through upper software to enable outputted MIPI signals to meet transmission time sequence requirements of an MIPI DPHY protocol. The device comprises a time sequence control interface module, an MIPI transmission control module, an MIPI signal generation module, an MIPI signal output module, an MIPI clock generation module, an MIPI data conversion module and an MIPI data generation module. The FPGA based method and the FPGA based device have the advantages that the transmission time sequences of an MIPI clock and data can be set respectively, and accordingly, positioning and searching of MIPI module problems are facilitated; transmission time sequence configuration of modules with different resolutions and transmission rates are supported, different parameters are adjusted and controlled in real time during signal transmission by the upper software, and optimization of an MIPI module is facilitated; characteristics of other conversion chips do not need to be known and used during research and development, production and test of the MIPI module, and implementation complexity is lowered.

Description

technical field [0001] The invention relates to the field of display and testing of MIPI liquid crystal modules, in particular to a method and device for realizing MIPI signal transmission adjustment based on FPGA. Background technique [0002] At present, the display screens used in many mobile phones and portable devices use MIPI video signal as the interface signal for receiving video data. MIPI signal has high transmission rate, low power consumption, high reliability, and supports various display resolutions and display modules. . [0003] When transmitting a video image, when transmitting a line or a frame of video data, it is transmitted in the form of a data stream in the HS (High Speed) state of the MIPI signal. When it is in the blanking area of ​​​​a line or a frame of image, the MIPI signal enters LP (Low Power) status. [0004] In order to ensure the reliability and low power consumption of video transmission, during the transmission process of video images in...

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Problems solved by technology

[0005] Due to the different transmission timing parameters and different resolutions, in the current MIPI signal implementation scheme (using a video source plus an external MIPI adapter chip), it is necessary to configure relevant parameters for the adapter chip, which is very important for the development of MIPI modules. , production, testing and other occasions require special personnel to be familiar with the performance and configuration of the adapter chip, which is very inconvenient to operate and makes the production efficiency and resource utilization efficiency low

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