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A method for making planar vdmos and planar vdmos

A planar and N-type technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as time-consuming, complicated process, and increased cost of planar VDMOS, so as to save manufacturing cost and reduce process complexity degree of effect

Active Publication Date: 2017-12-15
FOUNDER MICROELECTRONICS INT
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Obviously, in the prior art, the process of ion implantation doping and high-temperature annealing is used to reduce the JFET resistance of planar VDMOS. The process is complicated and time-consuming, thus increasing the cost of manufacturing planar VDMOS.

Method used

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  • A method for making planar vdmos and planar vdmos
  • A method for making planar vdmos and planar vdmos
  • A method for making planar vdmos and planar vdmos

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Embodiment Construction

[0034] Embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings and examples. The following examples are only used to illustrate the present invention, but can not be used to limit the scope of the present invention.

[0035] The method for fabricating a planar VDMOS will be described in detail below with an embodiment. Figure 4 The overall flow of the method is shown, and the specific steps are as follows:

[0036] Step S1: providing a substrate. Such as Figure 5 As shown, the provided substrate is an N-type substrate, such as a silicon substrate, a silicon germanium substrate, and the like.

[0037] Step S2: start to grow an epitaxial layer on the substrate, and start doping with a predetermined doping concentration at the same time. Such as Figure 5 As shown, the epitaxial layer grown on the N-type substrate is an N-type epitaxial layer. The growth method is, for example, a chemical vapor depositio...

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Abstract

The invention discloses a planar VDMOS making method which is characterized by comprising the following steps: providing a substrate; growing an epitaxial layer on the substrate, and carrying out doping at a predetermined doping concentration; increasing the doping concentration when the growth of the epitaxial layer is in a predetermined thickness range; restoring to the predetermined doping concentration and carrying out doping to complete the growth of the epitaxial layer after the growth of the epitaxial layer is beyond the predetermined thickness range; and making other structures of a planar VDMOS on the epitaxial layer to complete the making of the planar VDMOS. According to the invention, during planar VDMOS making, an ion implantation doping process and a high-temperature annealing drive process specially for making a low-resistance area of the epitaxial layer are omitted, so that the process complexity is reduced, and the manufacture cost is saved. The invention further discloses a planar VDMOS.

Description

technical field [0001] The invention belongs to the technical field of semiconductor chip manufacturing technology, and in particular relates to a method for manufacturing a planar vertical double-diffused metal-oxide semiconductor field-effect transistor (VDMOS) and a planar VDMOS. Background technique [0002] In semiconductor devices, junction field effect resistance (JFET resistance) is a resistance that varies with the depletion regions of two corresponding PN junctions. For trench (TRENCH) type VDMOS and planar (PLANAR) type VDMOS, due to the different device structures, in terms of on-resistance (Rdson), the performance difference between the two is mainly that planar VDMOS has JFET resistance, while trench type VDMOS does not. . Therefore, in terms of on-resistance, planar VDMOS is worse than trench VDMOS, resulting in poor performance of planar VDMOS in low-voltage and high-current applications. However, the trench VDMOS process is more complicated than the planar...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66712H01L29/7802
Inventor 马万里
Owner FOUNDER MICROELECTRONICS INT
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