Pixel bias circuit and control method for super large area array CMOS image sensor

Abstract

The invention discloses a pixel bias circuit and a control method for an oversized-area-array CMOS (complementary metal-oxide-semiconductor transistor) image sensor and aims to lower influences of ground wire parasitic resistance on pixel bias current precision and consistency and influences of pixel leakage current and line parasitic capacitance on row FPN (fixed pattern noise). The technical scheme includes that the pixel bias circuit comprises a first-stage bias current generating circuit, a second-stage bias current generating circuit and a third-stage bias current generating circuit which are connected in sequence, each of the first-stage bias current generating circuit, the second-stage bias current generating circuit and the third-stage bias current generating circuit is of a high-swing cascade structure with two circuits of equivalent current input, a voltage transmission mode is adopted in each of the first-stage bias current generating circuit, the second-stage bias current generating circuit and the third-stage bias current generating circuit, and a current transmission mode is adopted between every two of the first-stage bias current generating circuit, the second-stage bias current generating circuit and the third-stage bias current generating circuit.

Description

technical field [0001] The invention belongs to the technical field of CMOS image sensors, and in particular relates to a pixel bias circuit and a control method for super large area array CMOS image sensors. Background technique [0002] In the mainstream CMOS image sensor, the pixel structure mainly uses the source follower as the output device, and the pixel bias circuit is used as the current source load of the source follower to provide the pixel array with high-precision and high-consistency column current. , to ensure that the pixel array works normally and stably. In small-scale CMOS image sensors, the highest accuracy reported so far is the voltage path mode cascode structure pixel bias circuit. However, in CMOS image sensors with tens of millions of pixels and above, due to the increase in the power consumption of the pixel bias circuit and the increase in the parasitic resistance of the ground wire, the channel length modulation effect seriously affects the relat...

AI Technical Summary

Problems solved by technology

If the pixel bias circuit is used for a large area array pixel such as N is much greater than 64, the parasitic resistance 299-352 of the ground wire will produce a voltage drop, which will cause a large difference in the gate-source voltage of the common source transistor 235-298, resulting in output Each current I OUT The difference is large, and the output current consistency of each channel is poor

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