Full FIFO (first in, first out) circuit design method and universal test bench of method

Abstract

The invention discloses a full FIFO (first in, first out) circuit design method and a universal test bench of the method, relates to the field of large-scale integrated circuit design and simulation testing of the design, and aims to solve technical problems that existing integrated circuit chip interface modes are complex and lack universality, meanwhile, a universal integrated circuit chip test bench is lacking and the like. According to the full FIFO circuit design method, functional modules in a circuit are connected in series sequentially; each functional module comprises three parts, namely, an input end, a functional logic unit and an output end, the functional logic unit is arranged between the input end and the output end, the input end comprises a current-stage receiving state machine and a current-stage receiving FIFO circuit which are connected in series, and a sending end comprises a current-stage sending FIFO circuit and a current-stage sending state machine which are connected in series. The universal test bench of the full FIFO circuit design method comprises a test case parse module, a front end module, a back end module, message detection modules and error detection modules.

Description

technical field [0001] The invention relates to the technical field of large-scale integrated circuit design and simulation verification thereof, in particular to an FPGA or ASIC chip circuit design method and a general simulation verification platform suitable for step-by-step processing of digital signals. Background technique [0002] In today's rapidly changing market, whether the chip can be supplied as soon as possible will directly affect the market sales and price of the product. This requires designers to complete product design, testing and manufacturing as soon as possible. However, with the increase of chip integration and chip scale, design and verification become more complicated and require a longer period of time. Therefore, how to design and verify ASIC conveniently and quickly has become a problem of interest to technicians. [0003] From a design perspective, design reusability has been promoted in the industry for many years. The core idea of ​​reusable...

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Problems solved by technology

[0006] The present invention aims to solve the technical problems of the existing integrated circuit chip interface methods such as complexity, lack of versatility, and lack of a general integrated circuit chip verification platform, and provides a simple and universal interface method, and the system can be completed through a unified verification platform. Full FIFO circuit design method and its general verification platform for verification of all modules in

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