Semi-floating gate transistor of drain region embedding inversion layer and manufacturing method thereof

Abstract

The invention provides a semi-floating gate transistor of a drain region embedding inversion layer and a manufacturing method thereof. The transistor comprises a semiconductor substrate, a plane channel area, a source region, a drain region, a first insulating layer, a floating gate, a diffusion region, a second insulating layer, a control gate and a metal line, wherein the plane channel area is located in an active region of the semiconductor substrate; the source region and the drain region are located on two sides of the plane channel area respectively; the first insulating layer containing a floating gate opening is arranged on a surface of the drain region; the floating gate covers the floating gate opening and the first insulating layer; the diffusion region is arranged in the drain region below the floating gate opening; the second insulating layer covers the whole floating gate, parts of the source region, a rain region surface and the whole plane channel area; the control gate is located above the second insulating layer; the metal line is used to realize leading out of a transistor gate, a source electrode, a drain electrode and the substrate. The transistor is characterized in that a drain region embedding inversion layer which tunnels between a transistor channel region and a heavy doping drain region is embedded below the control gate in the drain region. In the invention, through adding the embedding inversion layer, doping concentration gradient distribution between an embedded tunneling lattice pipe channel and the drain region is optimized; an incidence rate of band-to-band tunneling is increased; a reading and writing speed of the semi-floating gate transistor is improved and electric leakage of the transistor is reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor memory. The invention relates to a semi-floating gate device (Semi-Floating Gate transistor) using a drain region embedded in an inversion layer and a manufacturing method. Background technique [0002] Memory is one of the basic core chips of electronic products. It is widely used in various electronic products, including mobile phones, mobile handheld products, etc. Among them, non-volatile memory (Nonvolatile memory, NVM) has the characteristics of long-term data storage in case of power failure. . The mainstream structure of the non-volatile memory in the prior art is the floating gate transistor. [0003] In order to further improve the performance of the floating gate semiconductor memory, the concept of a semi-floating gate transistor (Semi-Floating Gate Transistor, SFGT) is proposed. A window is opened between the drain region of the device and the insulating layer of the floating ...

AI Technical Summary

Problems solved by technology

[0011] 1) The incidence of inter-band tunneling embedded in TFETs is not high, resulting in a reduction in device storage speed

2) When inter-band tunneling occurs, the leakage current is large due to the bipolar effect of the embedded TFET

Images