A semi-floating gate device with a drain region embedded in an inversion layer and its manufacturing method

Abstract

The invention proposes a semi-floating gate device with a drain region embedded in an inversion layer and a manufacturing method thereof. The device includes: a semiconductor substrate, a planar channel region located in the active region of the semiconductor substrate, and source regions and The drain area has a first insulating layer with a floating gate opening on the surface of the drain area, covering the floating gate opening and the floating gate of the first insulating layer. There is a diffusion area in the drain area below the floating gate opening, and the second insulating layer covers the entire floating gate. The control gate is located above the second insulating layer on part of the surface of the source and drain regions and the entire planar channel area, and there are also metal connections to lead out the gate, source, drain and substrate of the device. The characteristic is that at the drain In the region, an inversion layer is embedded in the drain region between the channel region and the heavily doped drain region of the embedded tunneling transistor below the control gate. The present invention optimizes the doping concentration gradient distribution between the channel and the drain region of the embedded tunneling lattice tube by adding an embedded inversion layer, improves the occurrence rate of inter-band tunneling, improves the read and write speed of the semi-floating gate device, and reduces the device cost. Leakage.

Description

technical field [0001] The invention belongs to the technical field of semiconductor memory. The invention relates to a semi-floating gate device (Semi-Floating Gate transistor) using a drain region embedded in an inversion layer and a manufacturing method. Background technique [0002] Memory is one of the basic core chips of electronic products. It is widely used in various electronic products, including mobile phones, mobile handheld products, etc. Among them, non-volatile memory (Nonvolatile memory, NVM) has the characteristics of long-term data storage in case of power failure. . The mainstream structure of the non-volatile memory in the prior art is the floating gate transistor. [0003] In order to further improve the performance of the floating gate semiconductor memory, the concept of a semi-floating gate transistor (Semi-Floating Gate Transistor, SFGT) is proposed. A window is opened between the drain region of the device and the insulating layer of the floating ...

AI Technical Summary

Problems solved by technology

[0011] 1) The incidence of inter-band tunneling embedded in TFETs is not high, resulting in a reduction in device storage speed

2) When inter-band tunneling occurs, the leakage current is large due to the bipolar effect of the embedded TFET

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