Heterogeneous multi-core SoC design evaluation system

An evaluation system, heterogeneous multi-core technology, applied in computing, special data processing applications, instruments, etc., can solve problems such as prone to errors, low work efficiency, complicated technology, software and processes

Active Publication Date: 2015-09-09
BEIJING SMART LOGIC TECH CO LTD
View PDF4 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technologies, software and processes involved in the design of heterogeneous multi-core SoC architecture are very complicated
If only

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Heterogeneous multi-core SoC design evaluation system
  • Heterogeneous multi-core SoC design evaluation system
  • Heterogeneous multi-core SoC design evaluation system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013] The heterogeneous multi-core SoC design evaluation system provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0014] figure 1 It is a schematic diagram of a heterogeneous multi-core SoC design evaluation system provided by an embodiment of the present invention.

[0015] refer to figure 1 , the system includes a component abstract modeling module 10 , a design space definition module 20 , a performance index evaluation module 30 , a model training and exploration module 40 and an architecture optimization module 50 .

[0016] The component abstract modeling module 10 is used for performing abstract modeling on the master-slave components of the bus, wherein the master-slave components include functional components such as coprocessors, internal and external storage units, and high-speed IOs.

[0017] Here, the principle of the component abstract modeling module 10 is to focus on the conne...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a heterogeneous multi-core SoC design evaluation system. The system comprises an assembly abstract modeling module for performing abstract modeling for a master-slave assembly of a bus, a design space definition module for setting each variable and the value range corresponding to each variable according to the SoC design demand, a performance index evaluation module for forming a first SoC structure according to each variable and the value range as well as performing simulation evaluation and comprehensive evaluation of the first SoC structure so as to obtain performance indexes of the SoC, a model training and exploring module for performing model training by the machine learning algorithm according to the performance index and each variable so as to obtain a predication module or a classifying module, and a system structural optimizing module for selecting a second SoC structure through the predication module or the classifying module, wherein the master-slave assembly comprises a coprocessor. With the adoption of the system, the design and evaluation of a heterogeneous multi-core SoC system structure can be assisted to be done.

Description

technical field [0001] The invention relates to computer application technology, in particular to a heterogeneous multi-core SoC design evaluation system. Background technique [0002] With the continuous development of chip manufacturing technology and the increasing demand for multi-functional, high-efficiency, low-energy, and easy-to-carry chips in today's society, chips that blindly pursue high frequency, high capacity, and homogeneous multi-core in the past have encountered bottlenecks. In order to meet the new demands for integrated circuits in the new era, the International Technology Roadmap for Semiconductors (ITRS) proposed a new development goal for the industry - "More than Moore". ITRS believes that the development of integrated circuits should not be limited to "Moore's Law" and blindly pursue increasing the capacity of chips or reducing the volume of chips, but should focus on using different methods to provide consumers with more added value. Development in ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F17/50
Inventor 林忱杜学亮
Owner BEIJING SMART LOGIC TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products