EEPROM memory cell gate control signal generating circuit

Abstract

The invention discloses an EEPROM memory cell gate control signal generating circuit which comprises a high-voltage row decoding circuit and a plurality of word selection circuits, wherein the output of the high-voltage row decoding circuit is divided into two paths which are used for outputting first total word line voltage for providing positive erasing voltage and second total word line voltage for providing negative erasing voltage; the first total word line voltage and the second total word line voltage are input to each word selection circuit. Therefore, impact of positive erasing voltage on the gate oxide layers of NMOS transistors and impact of negative erasing voltage on PMOS transistors are avoided, and the number of MOS transistors used for isolating the gate oxide layers is decreased, that is, the circuit can be simplified, and the cost can be reduced.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to an EEPROM storage unit gate control signal generating circuit. Background technique [0002] Based on the EEPROM structure of the SONOS tube, the requirements for the gate voltage of the memory cell, that is, the word line voltage WLS, and the memory cell substrate VBULK are shown in Table 1: [0003] Table I [0004] [0005] Among them, VPOS is the positive voltage for erasing and writing, which is the positive high voltage required for erasing and programming, and VNEG is the negative voltage for erasing and writing, which is the negative high voltage required for erasing and programming. When programming, add VPOS and VNEG to the gate and substrate of the selected memory cell, respectively, for programming operation; add VNEG to the gate and substrate of unselected memory cells in the same column as the selected memory cell, and will not perform programming operation....

AI Technical Summary

Problems solved by technology

However, the drains of PMOS transistors P0 and P1 and NMOS transistors N0 and N1 cannot be directly connected together, otherwise when the drains of PMOS transistors P0 and P1 output VPOS, VNEG will appear on the gates of NMOS transistors N0 and N1, causing the NMOS transistor The voltage of the gate oxide layer of N0 and N1 is too high; and when the drains of NMOS transistors N0 and N1 output VNEG, VPOS will appear in the gate of PMOS transistor P0 or P1, so that the voltage of the gate oxide layer of PMOS transistor P0 or P1 too high

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