A base voltage control circuit for boost architecture
A technology for controlling circuit and base voltage, applied in electrical components, output power conversion devices, etc., can solve problems such as increasing the cost of architecture development, and achieve the effect of saving development costs, simplifying circuit design, and reducing chip size
Active Publication Date: 2018-02-06
SHANGHAI ORIENT CHIP TECH CO LTD
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Problems solved by technology
However, since an additional PMOS transistor is provided in the entire structure, and the PMOS transistor is located in the main high-current path, its chip size must be large to make its on-resistance Rds(on) small, thus increasing the related architecture development cost
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[0026] Below in conjunction with the drawings, preferred embodiments of the present invention are given and described in detail.
[0027] like Figure 5 , 6 As shown, the present invention is a base voltage control circuit 200 for a boost architecture, wherein the boost architecture includes a power PMOS transistor 100, which has a first pole Va connected to a voltage input terminal Vin and connected to a voltage The second pole Vb of the output terminal Vout (ie, the potential of the first pole Va is equal to the input voltage Vin, and the potential of the second pole Vb is equal to the output voltage Vout).
[0028] The circuit 200 of the present invention specifically includes:
[0029] The first resistor R1 and the second resistor R2 are connected in series between the first stage Va of the power PMOS transistor 100 and the ground, and the third resistor R3 is connected in series between the second pole Vb of the power PMOS transistor and the ground and the fourth resis...
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The present invention relates to a base voltage control circuit for a boosting architecture, the boosting architecture includes a power PMOS transistor, which has a first pole connected to a voltage input terminal and a second pole connected to a voltage output terminal, said The circuit includes: a voltage comparator, whose positive input terminal is connected to the first pole of the power PMOS transistor, and whose negative input terminal is connected to the second pole of the power PMOS transistor; a first level shifter; a second level converter; and the first to sixth PMOS tubes. The present invention judges the potential level of the first pole and the second pole of the power PMOS transistor in the boost architecture by using a voltage comparator, and correspondingly controls the switches of the first to sixth MOS transistors through the first and second level converters State, so as to control the base potential of the power PMOS transistor, by making it selectively the same potential as the first pole or the second pole of the power PMOS transistor under different states of the input voltage, and then control the first pole of the power PMOS transistor and the direction of the parasitic diode between the second pole to output zero potential.
Description
technical field [0001] The invention relates to a control framework applied to low-voltage and high-speed circuits, and in particular to a base voltage control circuit used in a boosting framework. Background technique [0002] At present, no matter whether it is an NMOS transistor or a PMOS transistor, it has a structural parasitic PN junction. For example, when the base and source of the PMOS transistor are connected to the same potential, there will be a parasitic PN junction from the drain to the source. Another example: when the base and source of the NMOS transistor are connected to the same potential, there will be a parasitic PN junction from the source to the drain. Therefore, in some charging (charger) or boost (boost) systems, due to the natural conditions of the boost architecture, at the moment of power-on (that is, when the input voltage Vin starts to input), there is a voltage output, that is, the output voltage Vout on the system It cannot completely reach t...
Claims
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IPC IPC(8): H02M1/08
Inventor 罗杰薛经纬
Owner SHANGHAI ORIENT CHIP TECH CO LTD