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Method and device for digital filtering and dejittering

A digital filtering and de-jittering technology, applied in the direction of pulse shaping, etc., can solve the problems of difficult design, poor effect, high power consumption, etc., and achieve the effect of simple structure, low power consumption, and filter out burrs

Active Publication Date: 2018-09-25
NO 24 RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method and device for digital filtering and de-jittering, which are used to solve the problem of using an analog filter circuit for de-jittering or glitches in the prior art due to the difficulty in design and the low performance. The problem of high consumption and large area to achieve poor results

Method used

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  • Method and device for digital filtering and dejittering
  • Method and device for digital filtering and dejittering
  • Method and device for digital filtering and dejittering

Examples

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Embodiment 1

[0046] The present invention adopts the working principle of the flip-flop 1. According to the flip-flop 1, the reset signal of the reset terminal R of the flip-flop 1 is different from the holding signal of the holding terminal S to filter and de-jitter the clock input signal flowing into the flip-flop 1 . Specifically:

[0047] When the reset terminal R of the flip-flop 1 is at a low level, the initial clock output signal of the flip-flop 1 is at a high level, and the first clock output signal Vout is at a high level, and the second clock output signal Vout_b is a low level; when the reset terminal R of the flip-flop 1 is high and its holding terminal S is low, the flip-flop 1 flips, making the first clock output signal Vout low, The second clock output signal Vout_b is at a high level.

[0048] At the same time, when the feedback clock output signal is input to the feedback control circuit 3, the closing and opening of the corresponding switch is controlled by the level of the...

Embodiment 2

[0061] The second clock input signal CLK_DB is an inverted and delayed output clock signal of the first clock input signal CLK, where the glitch Δt between the second clock input signal CLK_DB and the first clock input signal CLK must be It is satisfied that Δt is greater than zero, and the glitches of the second clock input signal CLK_DB are made to be the first clock input signal CLK without overlapping each other.

[0062] Such as Figure 4 Shown is an output timing diagram of a digital filtering and de-jittering device in an embodiment of the present invention.

Embodiment 3

[0064] When the input first clock input signal CLK is at a logic high level, the delay unit 4Delay_Cell outputs the second clock input signal CLK_DB at a logic low level, and the first clock output signal Vout is an output signal with jitter removed.

[0065] Assuming that the initial output state of the flip-flop 1 is logic zero, the output of the second inverter A2 is logic high, and the output of the first NAND gate Nand1 is connected to the input of the flip-flop 1, at this time the first The NAND gate Nand1 is at a logic low level, so that the output of the flip-flop 1 is forced to be at a logic high level, and the second clock output signal output by the second inverter A2 is at a logic low level. The first clock output signal output by the device A1 is at a logic high level, and the connection between the first NAND gate Nand1 and the flip-flop 1TRIGGER is then disconnected, and the delay unit 4Delay_Cell outputs the clock signal CLK_DB and the flip-flop 1TRIGGER is connec...

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Abstract

The invention provides a method and device for digital filtering and de-jittering. The method includes: filtering burrs in clock input signals to generate corresponding initial clock output signals, the clock input signals including a first clock input signal and a second clock input signal; performing reverse operation on the initial clock output signals to generate a first clock output signal and a second clock output signal; and according to the level of the first clock output signal and the second clock output signal that are fed back, switching on or switching off a corresponding switch, connecting with a clock input signal that a trigger corresponds to, and filtering jitter in the first clock input signal and / or the second clock input signal. The method for digital filtering and de-jittering realizes filtering and de-jittering of the clock input signals, and can also filter the burrs generated by the input signals in a process of digital filtering. The device is simple in structure and low in power dissipation, and is easy to realize, and not only can filtering and de-jittering be realized, but the load capacity of the device is also increased.

Description

Technical field [0001] The present invention relates to the technical field of the crossover of integrated circuits and interfaces, in particular to a method and a device for implementing de-jitter using digital filtering. Background technique [0002] In an integrated circuit, not only a crystal oscillator can generate a clock signal, but also a digital oscillator can also generate a clock signal. However, the clock signal generated by the oscillator can produce non-ideal waveforms such as glitches and jitter in some cases. In physical interface applications, due to mechanical and physical characteristics, for example, non-ideal jitter or glitches are generated during the opening and closing of a physical switch, a specific circuit needs to be installed to eliminate the aforementioned non-ideal glitch effects. [0003] In the prior art, analog filter circuits are usually used to eliminate glitches or jitter. However, the analog filter circuit does not achieve the above effect. T...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K5/01
Inventor 魏娟苏晨雷郎成付晓君刘伦才
Owner NO 24 RES INST OF CETC
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