Cache system and method

Abstract

Provided are a cache system and method applied in the field of processors before a processor core executes an instruction, storing the instruction and corresponding data in high-speed memory directly accessible by the processor core without the need of the processor core providing an instruction address or data address; according to feedback information generated when the processor core executes the instruction, directly controlling the high speed memory to provide instruction or data to the processor core, enabling the processor core to obtain needed instructions from the high speed memory almost every time, achieving an extremely high cache hit rate; in addition, further scheduling the transmission of instructions according to the program flow information stored in the cache system; and determining the instruction issuing time according to the instruction order and distance information, realizing multiple issuing of instructions.

Description

technical field [0001] The invention relates to the fields of computer, communication and integrated circuit. Background technique [0002] In a processor system that includes a pipeline, the pipeline is usually suspended due to factors such as Cache Miss, Control Hazard, and Data Hazard, thereby affecting the performance of the processor system. [0003] Cache misses generally fall into three categories: forced misses, conflict misses, and capacity misses. Using a set-associative cache structure and increasing the number of cached way groups can reduce conflict misses, but it is limited by power consumption and speed (for example, because the multi-way set-associative cache structure requires all way groups to be addressed by the same index content and tags Read and compare at the same time), the number of road groups is difficult to exceed a certain number. Existing cache prefetching techniques can usually solve some of the problems of missing conflicts and missing capac...

AI Technical Summary

Problems solved by technology

Since data read instructions and data storage instructions do not involve arithmetic and logic operations, the greater the proportion of such instructions, the lower the utilization rate of the processor's operation unit, and the less the processor's computing power can be fully utilized.

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