Fully differential increment sampling method of successive approximation type analog-digital converter

Abstract

The invention discloses a fully differential increment sampling method of a successive approximation type analog-digital converter. According to amplitude characteristic analysis of a neural signal, it is determined that during a non-active period of the signal, most amplitude values of the signal fall into a window of 16LSB, and therefore, a judging window is arranged to shield high-order redundancy conversion of the SAR ADC during the non-active period of the signal. When the signal is active, the amplitude change of the signal exceeds 16LSB and the ADC performs conversion from the high-order bits, so that the problem that the input signal amplitude needs to be limited for an input-tracking SAR ADC structure is solved. The increment sampling SAR ADC provided by the invention is a fully differential structure. The fully differential increment sampling method could effectively restrain common mode interference and even-order harmonic, improve accuracy of ADC conversion and solve the problems that the common mode disturbance of a signal-end structure is large and the noise of the even-order harmonic is obvious. Simultaneously, compared with a single-ended increment sampling structure, the fully differential structure has a doubled signal conversion range, thereby effectively broadening the range of input signals.

Description

【Technical field】 [0001] The invention relates to the technical field of analog-to-digital converters, in particular to a fully differential incremental sampling method of a successive approximation analog-to-digital converter. 【Background technique】 [0002] Low-power circuits have been the focus of circuit designs such as neural signal sensors and wireless sensor networks. Since the SAR ADC (successive approximation A / D converter, successive approximation analog-to-digital converter) has a simple structure and fewer analog modules, it can achieve extremely low power consumption, so it is especially suitable for low-power circuit design. The charge redistributed SAR ADC uses the capacitor array DAC arranged to the exponential power of 2, and realizes different quantization levels by switching capacitors with different weights between high and low reference levels, and makes this level eventually approach the sampling level signal to obtain quantified results. For an N-bit...

AI Technical Summary

Problems solved by technology

[0009] The purpose of the present invention is to provide a full differential incremental sampling method of successive approximation analog-to-digital converters, to solve the high-bit conversion redundancy problem encountered by SAR ADC and the deficiencies of existing solutions

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