Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Single measurement node simulation circuit fault diagnosis method

A technology for simulating circuit faults and diagnosing methods, applied in the direction of simulating circuit testing, measuring electricity, measuring electrical variables, etc., can solve the problem that the circuit cannot directly apply the characteristic factor of blind source separation technology.

Active Publication Date: 2015-11-11
HEFEI UNIV OF TECH
View PDF5 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the circuit with a single measurement node cannot directly apply the blind source separation technology to extract the characteristic factor

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Single measurement node simulation circuit fault diagnosis method
  • Single measurement node simulation circuit fault diagnosis method
  • Single measurement node simulation circuit fault diagnosis method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0034] The present invention will be described in detail below in conjunction with the drawings.

[0035] Reference figure 1 , A single measurement node analog circuit fault diagnosis method, including the following steps:

[0036] (1) Obtain a priori sample data vector under each failure mode: use computer simulation software to obtain each failure mode F of the analog circuit under test i Group M voltage sample vector V ij , I = 1, 2,..., N, j = 1, 2, 3,..., M, where N is the total number of circuit failure modes, i represents the circuit working in the i-th type of failure mode, and j is the collected group j Sample, V ij Represents the j-th group of voltage sample vectors collected when the circuit works in the i-th fault mode. in figure 1 Represented as: Collect the voltage sample vector of the M group of type 1 failure mode; Collect the voltage sample vector of the M group of type 2 failure mode; ...; Collect the voltage sample vector of the M group of type N failure mode. ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a single measurement node simulation circuit fault diagnosis method, comprising steps of obtaining prior sample data vectors under various fault modes, (2) calculating statistic average values of the prior samples under various fault modes, (3) decomposing the signal haar orthogonal wavelet filter set, extracting characteristic factors of the prior sample fault modes, (5) extracting characteristic factors of the fault mode to be detected, (6) calculating a correlation coefficient matrix and correlation degree measurement parameters between the characteristics factors of the fault mode to be detected and the characteristic factors of the prior sample fault modes, and (7) comparing the correlation degree measurement parameters and determining the fault mode according to the maximal correlation principle. The single measurement node simulation circuit fault diagnosis method disclosed by the invention converts single-path signals to multi-path signals under the condition that the original measurement information is not lost, extracts independent characteristic factors of the faulted mode, enables the characteristic factors of the faulted mode to reflect the changing situation of the circuit structure under various fault modes, studies correlated mode determination rule and finishes the successful classification of the circuit fault mode.

Description

Technical field [0001] The invention relates to a fault diagnosis method for a single measurement node analog circuit. Background technique [0002] The analog circuit fault diagnosis is essentially equivalent to the pattern recognition problem, and the key lies in the search for the relationship between feature extraction and pattern criterion function. Therefore, how to find the potential fault characteristic factors from the seemingly complicated measurement data, and based on this, to correctly judge and identify the fault mode, is called an important research topic in the field of analog circuit testing. [0003] After decades of development in analog circuit fault diagnosis, the existing achievements in this area are diverse, and new research results continue to emerge. Summarizing the various technologies used in the fault diagnosis process, the more widely used methods are based on statistical theory, wavelet analysis and fault feature extraction methods, and fault pattern...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G01R31/316
CPCG01R31/3161G01R31/316
Inventor 袁莉芬吴磊何怡刚孙业胜张朝龙龙英程珍袁志杰赵德勤
Owner HEFEI UNIV OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products