FPGA intra-IO sheet interconnecting digital circuit based on re-encryption algorithm

Abstract

The invention discloses an FPGA intra-IO sheet interconnecting digital circuit based on re-encryption algorithm. The FPGA intra-IO sheet interconnecting digital circuit comprises a sending end digital circuit, a receiving end digital circuit and a clock generation module, wherein the sending end digital circuit comprises a plaintext data generation logic, a first asynchronous FIFO, a head synchronous LFSR encryption module, a second asynchronous FIFO, an AES encryption module, a parallel-serial conversion module, a serializer and an OBUFDS module, and the receiving end digital circuit comprises a deseriallizer, an IBUFGDS module, a serial-parallel conversion module, a third asynchronous FIFO write control logic, a third asynchronous FIFO, an AES decryption module, a fourth asynchronous FIFO, a head synchronous LFSR decryption module and a plaintext data reception logic. Encryption and decryption of interconnected data transmission processes between FPGA virtual IO sheets are realized through stable and effective re-encryption algorithm.

Description

technical field [0001] The invention relates to the field of encryption communication, in particular to a FPGA virtual IO chip interconnection digital circuit based on a re-encryption algorithm. Background technique [0002] With the continuous growth of IC (Integrated Circuit Design abbreviation, which means integrated circuit) design requirements, the logical resource capacity of FPGA (Field-Programmable Gate Array, which means Field Programmable Gate Array) is also expanding. The latest Ultra-ScaleFPGA produced by Xilinx Up to 40 million logic gates. However, with the increasing complexity and scale of IC design, even Ultra-Scale may not be able to meet the needs of user IC design, which requires the interconnection of two or more FPGAs to meet user needs. However, due to the limited IO interface of the FPGA, the interconnection has caused another problem: the number of IO (abbreviation for Input / Output, which means input / output) interfaces is limited, so people have pro...

AI Technical Summary

Problems solved by technology

However, with the increasing complexity and scale of IC design, even Ultra-Scale may not be able to meet the needs of user IC design, which requires the interconnection of two or even multiple FPGAs to meet user needs

However, because of the limited IO interface of the FPGA, the interconnection has caused another problem: the number of IO (abbreviation for Input / Output, which means input / output) is limited, so the concept of virtual IO has been proposed.

[0003] In the existing technology, although there are some encryption schemes for inter-chip interconnection of FPGA, they are basically used for ordinary inter-chip transmission, and the inter-chip interconnection scheme of virtual IO cannot be realized, and the encryption method is single and there is no effective synchronization mechanism. The encryption effect is not high, and the security performance is reduced

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