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SAR ADC adopting low resolution DAC capacitor array and application method thereof

A capacitor array and low-resolution technology, applied in the field of SARADC, can solve the problem of increasing the complexity of the circuit layout required for capacitor array matching, and achieve the effects of shortening conversion time, avoiding conversion time, and stable and reliable circuits

Active Publication Date: 2015-12-09
HEFEI AICHUANGWEI ELECTRONIC TECH CO LTD
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Problems solved by technology

Using a split capacitor digital-analog array can reduce the power consumption of the capacitor array and switching capacitors, but this increases the matching requirements of the capacitor array and the complexity of the circuit layout

Method used

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  • SAR ADC adopting low resolution DAC capacitor array and application method thereof
  • SAR ADC adopting low resolution DAC capacitor array and application method thereof
  • SAR ADC adopting low resolution DAC capacitor array and application method thereof

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Embodiment Construction

[0040] Further describe the technical scheme of the present invention in detail below in conjunction with accompanying drawing:

[0041] This embodiment is a 2-bit / period SARADC structure, in which 2-bit interpolation and 8-bit capacitor digital-to-analog array are used. Therefore, the ADC can obtain 10-bit resolution, which realizes the use of low-resolution DAC capacitors. array implements a high-resolution SARADC.

[0042] Such as figure 2 As shown, this embodiment is composed of two 8-bit DAC arrays, three preamplifiers, five comparators and SAR control logic. An interpolation structure is adopted between the two DAC arrays, and one DAC array can be reduced compared with the traditional 2-bit / period SARADC structure. figure 2 The ratio of C1:C2:C3:C4 in the binary DAC array is 64:16:4:1, and a capacitive DAC array consists of 256 unit capacitors. During sampling, the inputs of the three preamplifiers are all connected to a common-mode voltage, and the bottom plate of ...

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Abstract

The invention discloses a SAR ADC adopting a low resolution DAC capacitor array and an application method thereof. The ADC comprises two DAC arrays, three preamplifiers, five comparators and a SAR control logic circuit. An interpolation structure is arranged between the two DAC arrays. Compared to the prior art, by using the ADC in the invention, one interpolation comparator is inserted between the two adjacent preamplifiers so that the number of capacitance digital-analog arrays can be reduced. A solution scheme of weighing a bandwidth and the resolution is provided for a multi-bit / periodic SAR ADC. By using the ADC and the method, there are the following advantages that for a high-precision SAR ADC design, usage of a large-scale DAC array can be avoided so that a capacitor DAC array only needs to satisfy thermal noise restraining demand.

Description

technical field [0001] The invention belongs to the field of analog-to-digital conversion integrated circuits, in particular to a SARADC using a low-resolution DAC capacitor array. Background technique [0002] Due to the increasing demand for high-quality multimedia and high-speed communication, the design of digital-to-analog converters (ADCs) is developing towards high precision, high sampling rate, and low power consumption. Among them, the design of low power consumption is particularly important for portable devices. The IEEE802.11 standard is also being developed towards higher bandwidth and greater signal-to-noise ratio (SNR). With the emergence of advanced CMOS processes (65nm, 40nm, 28nm, etc.), low-power high-performance analog-to-digital converters (ADCs) have become achievable. [0003] Since sampling and holding depend on high-performance operational amplifiers, as the channel length of CMOS process transistors becomes smaller and smaller, pipelined ADCs (Pip...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/38
Inventor 邱雷
Owner HEFEI AICHUANGWEI ELECTRONIC TECH CO LTD
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