Semiconductor substrate and thinning method thereof

Abstract

The invention discloses a semiconductor substrate and a thinning method. The thinning method comprises steps of providing a semiconductor substrate with a member structure formed in a front face, forming an opening area on the rim of the front face of the semiconductor substrate, pasting the front face of the semiconductor substrate with a lining sheet, thinning the back of the semiconductor substrate, wherein the thickness of the semiconductor substrate after thinning is smaller than or equal to the depth of the opening area, and separating the thinned semiconductor substrate from the lining sheet. An opening area is formed on the rim of the front side of the semiconductor substrate and the thickness of the semiconductor substrate after thinning is smaller than or equal to the depth of the opening area, so that even the size difference exists between the semiconductor substrate and the lining sheet or the aligning difference happens during the pasting process, the center area of the semiconductor substrate surrounded by the opening area is not affected. As a result, the breaches, the cracks or the collapsed edges are prevented on the edge of the semiconductor substrate after thinning.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor manufacturing technology, and particularly relates to a semiconductor substrate and a thinning method thereof. Background technique [0002] With the development of semiconductor technology, in order to obtain better parameters and functions, ultra-thin chip thickness is a current trend for special devices. Thinning can make the chip reach a certain thickness to meet the requirements of dicing, bonding and packaging processes. At the same time, the oxide layer and diffusion layer on the back are removed to ensure good contact on the back of the chip during soldering and reduce contact resistance and parasitic effects. Generally, in devices such as VDMOS (vertical double diffused metal-oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), three-dimensional integrated circuits (3DIC), and microelectromechanical systems (MEMS), when the front surface of the silic...

AI Technical Summary

Problems solved by technology

However, since semiconductor manufacturing equipment is designed according to the specific size of the silicon wafer, the diameter range error of most of the equipment is less than 0.5mm. Especially for precision equipment, the error range of the silicon wafer size is required to be smaller. If the size is larger than the maximum size range allowed by the equipment, it will not be processed

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