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Low surface roughness polishing pad

A technology for surface roughness and polishing pads, which is applied in the field of polishing pads and can solve problems such as changes in substrate uniformity

Inactive Publication Date: 2015-12-16
CABOT MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, uniformity can vary between substrates

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0029] This example illustrates the removal rate for silicon oxide exhibited by the inventive polishing pad as a function of the number of substrates polished using the inventive polishing pad.

[0030] A similar substrate comprising a blanket layer of silica derived from tetraethylorthosilicate was polished using a conventional polishing pad in combination with a polishing composition and a polishing pad according to an embodiment of the present invention. The polishing pad of the present invention is prepared using thermoplastic polyurethane resin (87A thermoplastic polyurethane resin, from Lubrizol, Wickcliffe, OH), the Shore D hardness (ShoreDhardness) of this polishing pad is 42D, and the average pore size is 25 to 45 microns, by confocal microscope The measured average surface roughness was 1.4 microns, and the elastic storage modulus (E') is shown in the table below.

[0031] surface

[0032] E' at 20°C

E' at 40°C

E' at 60°C

27.46Mpa

22.45Mp...

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PUM

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Abstract

The invention provides a polishing pad comprising a polishing pad body comprising a polishing surface, wherein the polishing body comprises pores, and wherein the polishing surface has a surface roughness of 0.1 [mu]m to 10 [mu]m.

Description

technical field [0001] The present invention relates to a polishing pad and a method of polishing a substrate; and in particular, the present invention relates to a polishing pad comprising a polishing pad body comprising a polishing surface, wherein the polishing body comprises pores, and Wherein the polished surface has a surface roughness of 0.1 microns to 10 microns. Background technique [0002] Chemical-mechanical polishing ("CMP") processes are used in the fabrication of microelectronic devices to form planar surfaces on semiconductor wafers, field emission displays, and many other microelectronic substrates. For example, the fabrication of semiconductor devices typically involves forming various process layers, selectively removing or patterning portions of those layers, and depositing additional process layers over the surface of a semiconductor substrate to form a semiconductor wafer. For example, the process layer may include an insulating layer, a gate oxide lay...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B24B37/24
CPCB24B37/205B24B37/26
Inventor J.奈尔
Owner CABOT MICROELECTRONICS CORP
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