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Semiconductor device including co-connected vertical cell strings

A technology of semiconductor, vertical part, applied in the field of three-dimensional semiconductor memory device and its manufacturing, which can solve the problems of expensive and difficult

Active Publication Date: 2018-12-07
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Further integration of such devices becomes more difficult (and more expensive) as patterning techniques approach practical limits
In any case, major developments in device integration of 2D memory cell arrays will require super-expensive processing equipment

Method used

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  • Semiconductor device including co-connected vertical cell strings
  • Semiconductor device including co-connected vertical cell strings
  • Semiconductor device including co-connected vertical cell strings

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0076] Figure 1A with Figure 1B is a perspective view and a plan view showing a semiconductor device according to a first embodiment of the inventive concept, Figure 1C is along Figure 1B The cross-sectional view taken along the line II'. also, Figure 1D is a schematic circuit diagram showing a cell array of a semiconductor device according to a first embodiment of the inventive concept.

[0077] refer to Figure 1A to Figure 1C, the semiconductor device may include a bit line BL on the substrate 100, a gate structure GS between the substrate 100 and the bit line BL, a common source line CSL between the gate structure GS and the bit line BL, and a pass through the gate Channel structure CS of structure GS. Each of the channel structures CS may be configured to connect a corresponding one of the bit lines BL to the common source line CSL. The semiconductor device may further include a contact plug PLG disposed between the gate structure GS and the bit line BL.

[00...

no. 2 example

[0114] Figure 7A with Figure 7B is a perspective view and a plan view showing a semiconductor device according to a second embodiment of the inventive concept, Figure 7C is along Figure 7B A cross-sectional view taken along the line II'. also, Figure 7D is a schematic circuit diagram showing a cell array of a semiconductor device according to a second embodiment of the inventive concept. In the following Figure 7A to Figure 7D In the description of , for the sake of brevity, previously referred to Figure 1A to Figure 1D Described elements may be denoted by similar or identical reference numerals without repeating their repeated descriptions.

[0115] refer to Figure 7A to Figure 7C , the semiconductor device may include a bit line BL on the substrate 100, a gate structure GS between the substrate 100 and the bit line BL, a common source line CSL between the gate structure GS and the bit line BL, and a pass through the gate Channel structure CS of structure GS. ...

no. 3 example

[0168] Figure 15A with Figure 15B is a perspective view and a plan view showing a semiconductor device according to a third embodiment of the inventive concept, Figure 15C is along Figure 15B A cross-sectional view taken along the line II'. in addition, Figure 15D is a schematic circuit diagram showing a cell array of a semiconductor device according to a third embodiment of the inventive concept. In the following Figure 15A to Figure 15D In the description of , for the sake of brevity, previously referred to Figure 1A to Figure 1D Described elements may be denoted by similar or identical reference numerals without repeating their repeated descriptions.

[0169] refer to Figure 15A to Figure 15C , the semiconductor device may include a bit line BL on the substrate 100, a gate structure GS between the substrate 100 and the bit line BL, a common source line CSL between the gate structure GS and the bit line BL, and a pass through the gate Channel structure CS of ...

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Abstract

The invention discloses a semiconductor device, which comprises: each bit line on a substrate; a gate structure between the substrate and the bit line; a common source line between the gate structure and the bit line; and connecting the bit line channel structure to the common source line. Each of the channel structures may include: a plurality of first vertical portions passing through the gate structure and connected to the bit line; second vertical portions passing through the gate structure and connected to the common source line; and horizontal A portion disposed between the substrate and the gate structure to connect the first vertical portion and the second vertical portion to each other.

Description

[0001] Cross References to Related Applications [0002] This patent application claims priority to Korean Patent Application No. 10-2014-0086182 filed with the Korean Intellectual Property Office on Jul. 9, 2014, the contents of which are incorporated herein by reference in their entirety. technical field [0003] Example embodiments of inventive concepts relate to semiconductor devices and methods of manufacturing the same, and in particular, to a three-dimensional semiconductor memory device having three-dimensionally arranged memory cells and methods of manufacturing the same. Background technique [0004] The continued development of highly integrated semiconductor devices is spurred in part by consumer demand for low cost, high performance products. Indeed, especially for semiconductor devices, increased device integration is a major factor in achieving price points that meet market demands. Conventionally, a semiconductor memory device includes a planar or two-dimens...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/1157
CPCG11C16/0483G11C16/12G11C16/3427G11C2216/02H10B43/10H10B43/40H10B43/27H10B51/20
Inventor 黄盛珉
Owner SAMSUNG ELECTRONICS CO LTD