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HDLC protocol controller based on FPGA chip

A protocol controller and controller technology, applied in the direction of data exchange through path configuration, electrical components, transmission systems, etc., can solve the problems of poor flexibility and limited storage capacity, and achieve low design and manufacturing costs, low power consumption, The effect of ensuring reliability

Inactive Publication Date: 2016-01-20
CRRC XIAN YONGEJIETONG ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a kind of HDLC protocol controller based on FPGA (field programmable gate array) chip, has solved the technical problem that existing protocol controller needs to rely on HDLC hardware protocol chip, use flexibility is poor, storage capacity is limited, Conducive to miniaturization of system scale and reduction of equipment cost

Method used

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  • HDLC protocol controller based on FPGA chip
  • HDLC protocol controller based on FPGA chip

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Embodiment Construction

[0018] figure 1 It is a system block diagram of a preferred embodiment of the present invention, wherein the main functions of each module are as follows:

[0019] (1) HDLC processing module

[0020] This module is mainly responsible for extracting the content of the frame information field from the received HDLC frame or encapsulating the frame information into HDLC frame format and sending it;

[0021] (2) DSP interface module

[0022] This module is responsible for the conversion of DSP bus timing and controller internal RAM and register read and write timing.

[0023] (3) Flash interface module

[0024] This module is responsible for the conversion of Flash read and write timing and frame processing module to Flash operation timing.

[0025] (4) Dual-port RAM (read, write)

[0026] The dual-port RAM includes RAM (read) and RAM (write). RAM (read) is responsible for temporarily storing the frame information (info) received by the HDLC processing module from the master ...

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Abstract

The invention relates to an HDLC (high-level data link control) protocol controller, in particular to an HDLC protocol controller based on an FPGA chip. The controller is integrated in the FPGA chip and comprises an HDLC processing module, a DSP port module and a dual-port RAM. The HDLC processing module is connected with a communication network main device and is used for receiving, processing and sending HDLC frame information. The DSP port module is connected with a DSP or a CPU and is used for switching the DSP bus timing sequence and inner read-write time sequence of the controller. The dual-port RAM is connected with the HDLC processing module and the DSP port module and used for receiving and temporarily storing the HDLC frame information between the communication network main device and the DSP. According to the invention, technical problems of poor use flexibility and limit storage capacity of a current protocol controller which requires an HDLC hardware protocol chip are solved, thereby facilitating miniaturization of system and reduction of device cost.

Description

technical field [0001] The invention relates to an HDLC (high-level data link control) protocol controller, in particular to an FPGA chip-based HDLC protocol controller. Background technique [0002] With the acceleration of the urbanization process, more and more social wealth and population are gathered in cities. Due to the inefficient use of road resources and the structural defects of urban roads, urban traffic problems have become increasingly prominent. To solve the traffic problem in the city, the development of rail transit has been put on the agenda. It has a better effect in solving the long-term traffic jam, and the rail transit has been greatly developed. [0003] Network communication is an important part of the normal operation of subway trains. If the network communication is not working properly, the host computer cannot transmit commands to the equipment of the train in real time and monitor the status of the equipment, and the entire train equipment cannot...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/40H04L29/06
Inventor 岳文开祁国俊杨伟李康乐李航刘辉
Owner CRRC XIAN YONGEJIETONG ELECTRIC CO LTD
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